Machine-Learning Defined Networking: Towards Intelligent Networks

With the advent of 5G technology and an ever-increasing traffic demand, today Communication Service Providers (CSPs) experience a progressive congestion of their networks. The operational complexity, the use of manual configuration, the static nature of current technologies together with fast-changing traffic profiles lead to: inefficient network utilization, over-provisioning of resources and very high Capital Expenditures (CapEx) and Operational Expenses (OpEx). This situation is forcing the CSPs to change their underlying network technologies, and have started to look at new technological solutions that increase the level of programmability, control, and flexibility of configuration, while reducing the overall costs related to network operations. Software Define Networking (SDN), Network Function Virtualization (NFV) and Machine Learning (ML) are accepted as effective solutions to reduce CapEx and OpEx and to boost network innovation. This chapter summarizes the content of my Ph.D. thesis, by presenting new ML-based approaches in order to efficiently optimize resources in 5G metro-core SDN/NFV networks. The main goal is to provide the modern CSP with intelligent and dynamic network optimization tools in order to address the requirements of increasing traffic demand and 5G technology.

Inductorless Frequency Synthesizers for Low-Cost Wireless

The quest for ubiquitous wireless connectivity, drives an increasing demand for compact and efficient means of frequency generation. Conventional synthesizer options, however, generally trade one requirement for the other, achieving either excellent levels of efficiency by leveraging LC-oscillators, or a very compact area by relying on ring-oscillators. This chapter describes a recently introduced class of inductorless frequency synthesizers, based on the periodic realignment of a ring-oscillator, that have the potential to break this tradeoff. After analyzing their jitter-power product, the conditions that ensure optimum performance are derived and a novel digital-to-time converter range-reduction technique is introduced, to enable low-jitter and low-power fractional-N frequency synthesis. A prototype, which implements the proposed design guidelines and techniques, has been fabricated in 65 nm CMOS. It occupies a core area of 0:0275 mm$$^{2}$$ 2 and covers the 1:6-to-3:0 GHz range, achieving an absolute rms jitter (integrated from 30 kHz-to-30 MHz) of 397 fs at 2:5 mW power. With a corresponding jitter-power figure-of-merit of −244 dB in the fractional-N mode, the prototype outperforms prior state-of-the-art inductorless frequency synthesizers.

Traffic Management in Networks with Programmable Data Planes

This brief includes a summary of the Ph.D. thesis entitled “Traffic management in networks with programmable data planes” and supervised by Prof. Antonio Capone. Software-Defined Networking (SDN) enables the configuration and operation of communications networks through open software programming interfaces providing an unprecedented flexibility in their dynamic reconfiguration and management. The thesis analyses the opportunities for traffic management provided by the SDN paradigm at different levels. Starting from the programmability at the control plane, we have designed a Traffic Engineering framework operating on the global view offered on top of the controller to proactively configure the network according to traffic measurements while limiting the number of reconfigurations. In order to deal with unexpected conditions such as network failures and congestion, the above centralized, global and proactive approach has been complemented by reactive and distributed approaches based on advanced stateful programmable data planes which enable a self-adaptation according to partial local information yielding to a more prompt and scalable reaction. All the solutions presented in the thesis have been evaluated with software prototypes based on research-oriented or production-ready open-source tools. Some of the extensions developed for these tools have been integrated as official open-source contributions.

Allowing a Real Collaboration Between Humans and Robots

Robotics researchers are spending many efforts in developing methodologies and techniques that allow robots to work side by side with humans, with the aim of improving the manufacturing processes. Such a level of interaction does not require just the safe coexistence in a common space, which is something completely achieved by the current state of the art. In scenarios like co-assemblies, humans and robots have to execute alternating tasks, with the aim of realizing a set of possible finite products. This requires the robots to adapt, synchronize and actively cooperate with the humans. This work will show that this goal can be reached by providing the cobots with three main abilities: recognizing the human behaviour, predicting the human actions and optimally planning the robotic ones.

Characterization and Modeling of Spin-Transfer Torque (STT) Magnetic Memory for Computing Applications

With the ubiquitous diffusion of mobile computing and Internet of Things (IoT), the amount of data exchanged and processed over the internet is increasing every day, demanding secure data communication/storage and new computing primitives. Although computing systems based on microelectronics steadily improved over the past 50 years thanks to the aggressive technological scaling, their improvement is now hindered by excessive power consumption and inherent performance limitation associated to the conventional computer architecture (von Neumann bottleneck). In this scenario, emerging memory technologies are gaining interest thanks to their non-volatility and low power/fast operation. In this chapter, experimental characterization and modeling of spin-transfer torque magnetic memory (STT-MRAM) are presented, with particular focus on cycling endurance and switching variability, which both present a challenge towards STT-based memory applications. Then, the switching variability in STT-MRAM is exploited for hardware security and computing primitives, such as true-random number generator (TRNG) and stochastic spiking neuron for neuromorphic and stochastic computing.

Frequency Synthesizers Based on Fast-Locking Bang-Bang PLL for Cellular Applications

The fractional-N frequency synthesis based on Digital Phase Locked Loop (DPLLs) has become a conventional design approach for the new radio wireless applications. The advantage of the digitally-intensive design style is the possibility to implement low-power and very accurate digital calibration techniques. Most of these algorithms run in the background tracking PVT variations and either relax or, in some cases, completely remove the performance limitations due to analog impairments. Moreover, the digital loop filter area is practically negligible with respect to the one in analog PLLs. These benefits become even more relevant in the scaled CMOS technology nodes. This chapter identifies the design parameters of a standard DPLL architecture and proposes a novel locking scheme to overcome the intrinsic limitations of the digital frequency synthesizers approach. To prove this new scheme a sub-6 GHz fractional-N synthesizer has been implemented in 65 nm CMOS. The synthesizer has an output frequency from 3.59 GHz to 4.05 GHz. The integrated output jitter is 182fs and the power consumption of 5.28 mW from 1.2 V power supply leads to a FoM of −247.5 dB. This topology exploits a novel locking technique that guarantee a locking time of 5.6 s, for a frequency step of 364 MHz, despite the use of a single bit phase detector.

Preplay Communication in Multi-Player Sequential Games: An Overview of Recent Results

The computational study of game-theoretic solution concepts is fundamental to describe the optimal behavior of rational agents interacting in a strategic setting, and to predict the most likely outcome of a game. Equilibrium computation techniques have been applied to numerous real-world problems. Among other applications, they are the key building block of the best poker-playing AI agents [5, 6, 27], and have been applied to physical and cybersecurity problems (see, e.g., [18, 20, 21, 30–32]).

One Step in-Memory Solution of Inverse Algebraic Problems

Machine learning requires to process large amount of irregular data and extract meaningful information. Von-Neumann architecture is being challenged by such computation, in fact a physical separation between memory and processing unit limits the maximum speed in analyzing lots of data and the majority of time and energy are spent to make information travel from memory to the processor and back. In-memory computing executes operations directly within the memory without any information travelling. In particular, thanks to emerging memory technologies such as memristors, it is possible to program arbitrary real numbers directly in a single memory device in an analog fashion and at the array level, execute algebraic operation in-memory and in one step. In this chapter the latest results in accelerating inverse operation, such as the solution of linear systems, in-memory and in a single computational cycle will be presented.

Velocity on the Web

A new generation of Web Applications is pushing the Web infrastructure to process data as soon as they arrive and before they are no longer valuable. However, the Web infrastructure as it is not adequate, and Stream Processing technologies cannot deal with heterogeneous data streams and events. To solve these issues, we need to investigate how to identify, represent, and process streams and events on the Web. In this chapter, we discuss the recent advancements for taming Velocity on the Web of Data without neglecting Data Variety. Thus, we present a Design Science research investigation that builds on the state of the art of Stream Reasoning and RDF Stream Processing. We present our research results, for representing and processing stream and events on the Web, and we discuss their potential impact.

Optimization-Based Control of Microgrids for Ancillary Services Provision and Islanded Operation

The ongoing environmental crisis is pushing the electrical sector towards a radical transformation, as the wide diffusion of renewable sources requires the power system to be more distributed, cooperative, and flexible, being each portion of the grid now able to produce and absorb power. This poses much more coordination challenges with respect to the traditional centralized system, largely sustained by fully controllable fossil-based power plants. In this context, microgrids, i.e. intelligent small-scale grids equipped with distributed energy resources and smart loads, are considered as the fundamental bricks of this future paradigm. This is due to the opportunity of coordinating co-located sources and loads, and to the microgrids extreme flexibility, as they can be operated either connected to the main grid or in islanded mode. The contribution of this doctoral research consists in the design of dedicated control architectures for ensuring the efficient and secure operation of microgrids in these two modes, characterized by different challenges and opportunities.