SLAM: SLice And Merge - Effective Test Generation for Large Systems

2013 ◽  
pp. 151-165
Author(s):  
Tali Rabetti ◽  
Ronny Morad ◽  
Alex Goryachev ◽  
Wisam Kadry ◽  
Richard D. Peterson
Keyword(s):  
Test Generation ◽  
Large Systems

An Introductory Study on an Architecture-Based Software Product Line Test Generation Method

2019 ◽  
Vol 29 (08) ◽  
pp. 1071-1089
Author(s):  
Jihyun Lee
Keyword(s):  
Test Generation ◽  
Software Product Line ◽  
Product Line ◽  
Multiple Products ◽  
Product Line Architecture ◽  
Testing Stage ◽  
Software Product ◽  
Implementation Under Test ◽  
Line Test ◽  
Large Systems

Architecture-based testing allows test engineers to focus on the structure of complicated software and the interactions between software components that constitute the architecture of a software product. By observing and controlling the connections and interactions between components of complex or large systems during software testing, architecture-based testing can detect and localize such faults at those locations. The complexity of software product line testing is high because an implementation under test contains variability given the different binding times and is used by multiple products. This paper introduces how architecture-based testing is applied to test generation for a software product line and examines the strengths of the proposed method against existing software product line testing methods. The paper also illustrates the use of product line architecture and architectural artifacts to generate product line interaction tests. It was found that architecture-based testing can be applied to software product line test generation by tailoring it to deal with variability and product-line specific processes. The results of a comparison with existing methods show that architecture-based software product line test generation provides better capabilities in terms of variability in the testing stage, the explicit formation and application of binding, test coverage, and architectural awareness.

Low Power and High Speed Sequential Circuits Test Architecture

2019 ◽  
Vol 12 ◽  
Author(s):  
Ahmed K. Jameil ◽  
Yasir Amer Abbas ◽  
Saad Al-Azawi
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Test Generation ◽  
High Speed ◽  
Fir Filter ◽  
Sequential Circuits ◽  
Fir Filters ◽  
Design Verification ◽  
Sequential Circuit ◽  
Generation Algorithm

Background: The designed circuits are tested for faults detection in fabrication to determine which devices are defective. The design verification is performed to ensure that the circuit performs the required functions after manufacturing. Design verification is regarded as a test form in both sequential and combinational circuits. The analysis of sequential circuits test is more difficult than in the combinational circuit test. However, algorithms can be used to test any type of sequential circuit regardless of its composition. An important sequential circuit is the finite impulse response (FIR) filters that are widely used in digital signal processing applications. Objective: This paper presented a new design under test (DUT) algorithm for 4-and 8-tap FIR filters. Also, the FIR filter and the proposed DUT algorithm is implemented using field programmable gate arrays (FPGA). Method: The proposed test generation algorithm is implemented in VHDL using Xilinx ISE V14.5 design suite and verified by simulation. The test generation algorithm used FIR filtering redundant faults to obtain a set of target faults for DUT. The fault simulation is used in DUT to assess the benefit of test pattern in fault coverage. Results: The proposed technique provides average reductions of 20 % and 38.8 % in time delay with 57.39 % and 75 % reductions in power consumption and 28.89 % and 28.89 % slices reductions for 4- and 8-tap FIR filter, respectively compared to similar techniques. Conclusions: The results of implementation proved that a high speed and low power consumption design can be achieved. Further, the speed of the proposed architecture is faster than that of existing techniques.

scholarly journals Delay-Dependent Robust Stabilization for Nonlinear Large Systems via Decentralized Fuzzy Control

2011 ◽  
Vol 2011 ◽  
pp. 1-20 ◽  
Author(s):  
Chun-xia Dou ◽  
Zhi-sheng Duan ◽  
Xing-bei Jia ◽  
Xiao-gang Li ◽  
Jin-zhao Yang ◽  
...  
Keyword(s):  
Time Delay ◽  
Fuzzy Control ◽  
Upper Bound ◽  
Time Delays ◽  
Sufficient Conditions ◽  
Large System ◽  
Disturbance Attenuation ◽  
Robust Controller ◽  
Large Systems ◽  
Delay Dependent

A delay-dependent robust fuzzy control approach is developed for a class of nonlinear uncertain interconnected time delay large systems in this paper. First, an equivalent T–S fuzzy model is extended in order to accurately represent nonlinear dynamics of the large system. Then, a decentralized state feedback robust controller is proposed to guarantee system stabilization with a prescribedH∞disturbance attenuation level. Furthermore, taking into account the time delays in large system, based on a less conservative delay-dependent Lyapunov function approach combining with linear matrix inequalities (LMI) technique, some sufficient conditions for the existence ofH∞robust controller are presented in terms of LMI dependent on the upper bound of time delays. The upper bound of time-delay and minimizedH∞performance index can be obtained by using convex optimization such that the system can be stabilized and for all time delays whose sizes are not larger than the bound. Finally, the effectiveness of the proposed controller is demonstrated through simulation example.

scholarly journals Monitoring and Control of Large Systems with MonALISA

Queue ◽  
2009 ◽  
Vol 7 (6) ◽  
pp. 40-49
Author(s):  
Iosif Legrand ◽  
Ramiro Voicu ◽  
Catalin Cirstoiu ◽  
Costin Grigoras ◽  
Latchezar Betev ◽  
...  
Keyword(s):  
Monitoring And Control ◽  
Large Systems ◽  
And Control
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