High Speed VLSI Architecture for Finding the First W Maximum/Minimum Values

2015 ◽  
pp. 35-41
Author(s):  
Guoping Xiao ◽  
Waqar Ahmad ◽  
Syed Azhar Ali Zaidi ◽  
Massimo Ruo Roch ◽  
Giovanni Causapruno
Keyword(s):  
High Speed ◽  
Vlsi Architecture ◽  
Maximum Minimum

scholarly journals VLSI ARCHITECTURE OF PARALLEL MULTIPLIER– ACCUMULATOR BASED ON RADIX-2 MODIFIED BOOTH ALGORITHM

2012 ◽  
pp. 40-46
Author(s):  
Mr.M.V. Sathish ◽  
Mrs. Sailaja
Keyword(s):  
Signal Processing ◽  
High Speed ◽  
High Performance ◽  
Vlsi Architecture ◽  
Clock Frequency ◽  
Parallel Multiplier ◽  
Hybrid Type ◽  
Standard Design ◽  
Overall Performance ◽  
And Performance

A new architecture of multiplier-andaccumulator (MAC) for high-speed arithmetic. By combining multiplication with accumulation and devising a hybrid type of carry save adder (CSA), the performance was improved. Since the accumulator that has the largest delay in MAC was merged into CSA, the overall performance was elevated. The proposing method CSA tree uses 1’s-complement-based radix-2 modified Booth’s algorithm (MBA) and has the modified array for the sign extension in order to increase the bit density of the operands. The proposed MAC showed the superior properties to the standard design in many ways and performance twice as much as the previous research in the similar clock frequency. We expect that the proposed MAC can be adapted to various fields requiring high performance such as the signal processing areas.

High-Speed Area-Efficient VLSI Architecture of Three-Operand Binary Adder

2020 ◽  
Vol 67 (11) ◽  
pp. 3944-3953
Author(s):  
Amit Kumar Panda ◽  
Rakesh Palisetty ◽  
Kailash Chandra Ray
Keyword(s):  
High Speed ◽  
Vlsi Architecture ◽  
Area Efficient

VLSI Architecture for Robust Speech Recognition Systems and its Implementation on a Verification Platform

2005 ◽  
Vol 17 (4) ◽  
pp. 447-455 ◽  
Author(s):  
Shingo Yoshizawa ◽  
◽  
Noboru Hayasaka ◽  
Naoya Wada ◽  
Yoshikazu Miyanaga
Keyword(s):  
Speech Recognition ◽  
High Speed ◽  
Vlsi Architecture ◽  
Cmos Technology ◽  
Recognition System ◽  
Robust Speech Recognition ◽  
Speech Recognition System ◽  
Circuit Performance ◽  
Field Programmable ◽  
Testing Environments

This paper presents a VLSI architecture for a robust speech recognition system that enables high-speed, low-power operation. The proposed architecture improves recognition accuracy in noisy environments and realizes short-time response by implementing parallel and pipeline processing. We demonstrate improved processing time and power consumption by evaluating circuit performance in 0.25-μm CMOS technology. We also detail a verification platform that helps users implement our hardware-based robust speech recognition system. The verification platform facilitates software conversion to hardware and promptly provides testing environments on field-programmable gate arrays.

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