Implementation of the AES Algorithm for a Reconfigurable, Bit Serial, Fully Pipelined Architecture

AbstractAs the technology is growing day by day, information security plays a very important role in our lives. In order to protect the information, several cryptographic algorithms have been proposed. The aim of this paper is to present an effective Advanced Encryption Standard (AES) architecture to achieve high throughput for security applications. The Parallel Sub-Pipelined architecture (PSP) is proposed in order to obtain high throughput. The proposed architecture is also compared with loop unrolled, pipelined, sub-pipelined, parallel and parallel pipelined architecture in terms of throughput. The AES algorithm using Parallel Sub-Pipelined architecture was prototyped in FPGA (Field Programmable Gate Array) and ASIC (Application Specific Integrated Circuit).The proposed architecture yielded a throughput of 59.59 Gbps at a frequency of 450.045 MHz on FPGA Virtex XC6VLX75T which is higher than the throughput yielded in other architectures. In ASIC 0.13 µm technology, the proposed architecture yielded a throughput of 25.60 Gbps and in 0.18 µm, it yielded a throughput of 20.56 Gbps.

Download Full-text

Design of AES Pipelined Architecture for Image Encryption/Decryption Module

International Journal of Reconfigurable and Embedded Systems (IJRES) ◽

10.11591/ijres.v3.i3.pp114-118 ◽

2014 ◽

Vol 3 (3) ◽

pp. 114

Author(s):

Pravin V. Kinge ◽

S.J. Honale ◽

C.M. Bobade

Keyword(s):

Image Encryption ◽

Integrated Circuit ◽

High Speed ◽

Transmission Rate ◽

Image Data ◽

Limited Bandwidth ◽

Encrypted Image ◽

Aes Algorithm ◽

Pipelined Architecture ◽

Encryption And Decryption

The relentless growth of Internet and communication technologies has made the extensive use of images unavoidable. The specific characteristics of image like high transmission rate with limited bandwidth, redundancy, bulk capacity and correlation among pixels makes standard algorithms not suitable for image encryption. In order to overcome these limitations for real time applications, design of new algorithms that require less computational power while preserving a sufficient level of security has always been a subject of interest. Here Advanced Encryption Standard (AES),as the most widely used encryption algorithm in many security applications. AES standard has different key size variants, where longer bit keys provide more secure ciphered text output. The available AES algorithm is used for data and it is also suitable for image encryption and decryption to protect the confidential image from an unauthorized access. This project proposes a method in which the image data is an input to Pipelined AES algorithm through Textio, to obtain the encrypted image. and the encrypted image is the input to Pipelined AES Decryption to get the original image. This project proposed to implement the 128,192 & 256 bit Pipelined AES algorithm for image encryption and decryption, also to compare the latency , efficiency, security, frequency & throughput . The proposed work will be synthesized and simulated on FPGA family of Xilink ISE 13.2 and Modelsim tool respectively in Very high speed integrated circuit Hardware Description Language.

Download Full-text