How to Do Social Simulation in Logic: Modelling the Segregation Game in a Dynamic Logic of Assignments

Multi-Agent-Based Simulation XII - Lecture Notes in Computer Science ◽

10.1007/978-3-642-28400-7_5 ◽

2012 ◽

pp. 59-73 ◽

Cited By ~ 1

Author(s):

Benoit Gaudou ◽

Andreas Herzig ◽

Emiliano Lorini ◽

Christophe Sibertin-Blanc

Keyword(s):

Dynamic Logic ◽

Social Simulation

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GAME SOCIAL SIMULATION MODELING IN TRAINING OF PERSONNEL FOR INNOVATIVE ECONOMY

Профессиональное образование в современном мире ◽

10.15372/pemw20170224 ◽

2017 ◽

Keyword(s):

Simulation Modeling ◽

Social Simulation ◽

Innovative Economy ◽

Training Of Personnel

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Modelling the effects of social networks in interventions aimed at reducing meat consumption using a social simulation

10.26226/morressier.5ef37080b2a27f760262bb63 ◽

2020 ◽

Author(s):

Andrea Scalco ◽

Jennie Macdiarmid ◽

Stephen Whybrow ◽

Graham Horgan

Keyword(s):

Social Networks ◽

Meat Consumption ◽

Social Simulation

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Low Power Wide Fan-in Domino OR Gate Using CN-MOSFETs

International Journal of Sensors Wireless Communications and Control ◽

10.2174/2210327909666190207163639 ◽

2020 ◽

Vol 10 (1) ◽

pp. 55-62

Author(s):

Deepika Bansal ◽

Bal Chand Nagar ◽

Brahamdeo Prasad Singh ◽

Ajay Kumar

Keyword(s):

Power Consumption ◽

High Performance ◽

Dynamic Logic ◽

Clock Frequency ◽

Charge Sharing ◽

Benchmark Circuit ◽

Domino Circuit ◽

Power Delay Product ◽

Domino Circuits ◽

Or Gate

Background & Objective: In this paper, a modified pseudo domino configuration has been proposed to improve the leakage power consumption and Power Delay Product (PDP) of dynamic logic using Carbon Nanotube MOSFETs (CN-MOSFETs). The simulations for proposed and published domino circuits are verified by using Synopsys HSPICE simulator with 32nm CN-MOSFET technology which is provided by Stanford. Methods: The simulation results of the proposed technique are validated for improvement of wide fan-in domino OR gate as a benchmark circuit at 500 MHz clock frequency. Results: The proposed configuration is suitable for cascading of the high performance wide fan-in circuits without any charge sharing. Conclusion: The performance analysis of 8-input OR gate demonstrate that the proposed circuit provides lower static and dynamic power consumption up to 62 and 40% respectively, and PDP improvement is 60% as compared to standard domino circuit.

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