EMC Robust Design for Smart Power High Side Switches

A multi trench analog+logic protection (M-TRAP) for substrate crosstalk prevention in a 0.25 /spl mu/m smart power platform with 100V high-side capability

Proceedings of the 16th International Symposium on Power Semiconductor Devices & IC's ◽

10.1109/wct.2004.240347 ◽

2004 ◽

Cited By ~ 11

Author(s):

Parthasarathy ◽

Khemka ◽

Zhu ◽

Puchades ◽

Roggenbauer ◽

...

Keyword(s):

Smart Power ◽

High Side ◽

Analog Logic

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Hot-Carrier Reliability of High Side NDMOS in Smart Power SOI Technologies

Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005. ◽

10.1109/ispsd.2005.1487961 ◽

2005 ◽

Cited By ~ 2

Author(s):

Stefan Schwantes Franz Dietz

Keyword(s):

Smart Power ◽

Hot Carrier ◽

High Side

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Methodology to Quantify Impact of Package Delamination on Performance of High-Side Smart Power Switch Design

International Symposium on Microelectronics ◽

10.4071/2380-4505-2020.1.000015 ◽

2020 ◽

Vol 2020 (1) ◽

pp. 000015-000020

Author(s):

Min Chu ◽

Jie Chen ◽

Abidur Rahman ◽

Rajen Murugan

Keyword(s):

Electrical Performance ◽

Diagnostic Feature ◽

Electromagnetic Modeling ◽

Smart Power ◽

Modeling Methodology ◽

Power Switch ◽

High Side ◽

Die Attach ◽

Power Switches ◽

The Impact

Abstract Generally, IC packages with exposed pads have excellent thermal and electrical performance – assuming high fidelity and integrity of die attach material. However, reliability challenges associated with die attach impacts electrical performance of vertical power FETs for high-side power switches. As such, it is critical to quantify the impact of these challenges on high-side power switches operation, so that their protection and diagnostic feature circuitries can be properly designed for mission critical applications. In this paper we present on a package and PCB co-modeling methodology that was developed to assess impact of die attach integrity on performance of high-side power switch designs. We explain how electrical co-optimization of the system (viz. FET-Package-PCB) interactions, was achieved through a coupled circuit-to-electromagnetic modeling, simulation, and analysis methodology. Silicon laboratory measurements data that validate the modeling methodology will be presented.

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