A SPICE MODEL OF THE PEO-PANI MEMRISTOR

The memristor is a novel circuit element which is capable of maintaining an activity-dependent nonvolatile resistance and is therefore a candidate for use in next-generation storage and logic circuits. In this article, we present a model of the PEO-PANI memristor for use in the SPICE circuit simulation program which is especially suited to analog logic applications. Two variants are presented herein; accompanying each is a short description that explains any design decisions made, as well as elucidating on preferred simulation settings. It is shown that the model accurately replicates corresponding experimental results found in the literature. Simple simulations are used to show the suitability of each variant to specific experimental usage. Appendices contain verbatim implementations of the SPICE models.

Failure Localization & Design Debug on Mixed-Mode ICs by Using the Dynamic Laser Stimulation Techniques

Soft defect localization techniques based on laser stimulation have become key techniques for a wide range of FA/debug issues. In this paper, we demonstrate the ability of these techniques to solve critical design issue in mixed-mode device for automotive application which includes analog, logic, RF and power. Utilizing a wide range of laser stimulation techniques, we have determined the most efficient approach for this device to achieve the shortest cycle time. We have established a clear link between fault isolation by laser stimulation techniques and the abnormal behavior of the device with relevant and complete simulation at transistor level.