Design and Analysis of Single Precision Floating Point Multiplication with Vedic Mathematics Using Different Techniques

Multiplication of floating point(FP) numbers is greatly significant in many DSP applications. The performance of the DSP’s is substantially decided by the speed of the multipliers used. This paper proposes the design and implementation of IEEE 754 standard single precision FP multiplier using Verilog, synthesized and simulated in Xilinx ISE10.1. Urdhva Triyagbhyam Sutra of Vedic mathematics is used for the unsigned mantissa calculation. The design implements floating point multiplication with sign bit and exponent calculations. The proposed design is achieved high speed with minimum delay of 3.997ns.Multiplication of floating point(FP) numbers is greatly significant in many DSP applications. The performance of the DSP’s is substantially decided by the speed of the multipliers used. This paper proposes the design and implementation of IEEE 754 standard single precision FP multiplier using Verilog, synthesized and simulated in Xilinx ISE10.1. Urdhva Triyagbhyam Sutra of Vedic mathematics is used for the unsigned mantissa calculation. The design implements floating point multiplication with sign bit and exponent calculations. The proposed design is achieved high speed with minimum delay of 3.997ns.

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Research on IEEE 754 Standard Single Precision Floating Point Multipliers Designed using Urdhva Triyagbhyam Sutra of Vedic Mathematics

International Journal of Recent Technology and Engineering - 2 ◽

10.35940/ijrte.b1382.0982s1119 ◽

2019 ◽

Vol 8 (2S11) ◽

pp. 2990-2993

Keyword(s):

Floating Point ◽

Double Precision ◽

Single Precision ◽

Vedic Mathematics ◽

Quadruple Precision

Duplication of the coasting element numbers is the big activity in automated signal handling. So the exhibition of drifting problem multipliers count on a primary undertaking in any computerized plan. Coasting factor numbers are spoken to utilizing IEEE 754 modern day in single precision(32-bits), Double precision(sixty four-bits) and Quadruple precision(128-bits) organizations. Augmentation of those coasting component numbers can be completed via using Vedic generation. Vedic arithmetic encompass sixteen wonderful calculations or Sutras. Urdhva Triyagbhyam Sutra is most usually applied for growth of twofold numbers. This paper indicates the compare of tough work finished via exceptional specialists in the direction of the plan of IEEE 754 ultra-modern-day unmarried accuracy skimming thing multiplier the usage of Vedic technological statistics.

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NULL Convention Floating Point Multiplier

The Scientific World JOURNAL ◽

10.1155/2015/749569 ◽

2015 ◽

Vol 2015 ◽

pp. 1-10 ◽

Cited By ~ 1

Author(s):

Anitha Juliette Albert ◽

Seshasayanan Ramachandran

Keyword(s):

High Precision ◽

Dynamic Range ◽

Digital Signal ◽

High Dynamic Range ◽

Floating Point ◽

Single Precision ◽

Critical Part ◽

Point Multiplication ◽

Null Convention Logic ◽

High Dynamic

Floating point multiplication is a critical part in high dynamic range and computational intensive digital signal processing applications which require high precision and low power. This paper presents the design of an IEEE 754 single precision floating point multiplier using asynchronous NULL convention logic paradigm. Rounding has not been implemented to suit high precision applications. The novelty of the research is that it is the first ever NULL convention logic multiplier, designed to perform floating point multiplication. The proposed multiplier offers substantial decrease in power consumption when compared with its synchronous version. Performance attributes of the NULL convention logic floating point multiplier, obtained from Xilinx simulation and Cadence, are compared with its equivalent synchronous implementation.

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Floating Point Multiplication Based on Schonhage Strassen Algorithm

International Journal of Engineering & Technology ◽

10.14419/ijet.v7i2.20.11734 ◽

2018 ◽

Vol 7 (2.20) ◽

pp. 14

Author(s):

B Srikanth ◽

M Siva Kumar ◽

K Hari Kishore

Keyword(s):

Fixed Point ◽

Real Time ◽

Floating Point ◽

Single Precision ◽

Point Multiplication ◽

Multiplication Algorithm ◽

Integer Multiplication

In this paper, the single precision float point multiplication is performed using the Schonhage Strassen Algorithm. There are several types of floating point multiplications like Karatsubha and Toom cook. The Schonhage Strassen algorithm is conventionally a fixed point integer multiplication algorithm. The main advantage of the Schonhage Strassen multiplication is that, the multiplication of integer values greater than 5 digits ranging from 2215 to 2217 bit values proves to be efficient. The validation of the proposed floating point multiplication is done using FPGA real time implementation. The analysis of parameters like area and power are evaluated.

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Design and Implementation of FPU for Optimised Speed

International Journal of Engineering and Advanced Technology - Regular Issue ◽

10.35940/ijeat.c6444.029320 ◽

2020 ◽

Vol 9 (3) ◽

pp. 3922-3933

Keyword(s):

Energy Efficient ◽

High Speed ◽

Software Tool ◽

Digital Signal ◽

Floating Point ◽

Double Precision ◽

Arithmetic Unit ◽

Single Precision ◽

Point Multiplication ◽

Floating Point Unit

Currently, each CPU has one or additional Floating Point Units (FPUs) integrated inside it. It is usually utilized in math wide-ranging applications, such as digital signal processing. It is found in places be established in engineering, medical and military fields in adding along to in different fields requiring audio, image or video handling. A high-speed and energy-efficient floating point unit is naturally needed in the electronics diligence as an arithmetic unit in microprocessors. The most operations accounting 95% of conformist FPU are multiplication and addition. Many applications need the speedy execution of arithmetic operations. In the existing system, the FPM(Floating Point Multiplication) and FPA(Floating Point Addition) have more delay and fewer speed and fewer throughput. The demand for high speed and throughput intended to design the multiplier and adder blocks within the FPM (Floating point multiplication)and FPA(Floating Point Addition) in a format of single precision floating point and double-precision floating point operation is internally pipelined to achieve high throughput and these are supported by the IEEE 754 standard floating point representations. This is designed with the Verilog code using Xilinx ISE 14.5 software tool is employed to code and verify the ensuing waveforms of the designed code

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