Reliability Modelling of a Typical Peripheral Component Interconnect (PCI) System with Dynamic Reliability Modelling Diagram

2019 ◽  
pp. 1569-1576
Author(s):  
Guan Yi ◽  
Zhao Jiacong
Keyword(s):  
Dynamic Reliability ◽  
Reliability Modelling ◽  
Peripheral Component Interconnect

Dynamic reliability analysis of mechanical system with wear and vibration failure modes

2021 ◽  
Vol 163 ◽  
pp. 104385
Author(s):  
We Wang ◽  
Gang Shen ◽  
Yimin Zhang ◽  
Zhencai Zhu ◽  
Changyou Li ◽  
...  
Keyword(s):  
Mechanical System ◽  
Reliability Analysis ◽  
Failure Modes ◽  
Dynamic Reliability

scholarly journals A 1.93-pJ/Bit PCI Express Gen4 PHY Transmitter with On-Chip Supply Regulators in 28 nm CMOS

Electronics ◽  
2021 ◽  
Vol 10 (1) ◽  
pp. 68
Author(s):  
Woorham Bae ◽  
Sung-Yong Cho ◽  
Deog-Kyoon Jeong
Keyword(s):  
Finite Impulse Response ◽  
Cmos Process ◽  
Pci Express ◽  
Fully Integrated ◽  
Peripheral Component Interconnect ◽  
Low Power Cmos ◽  
On Chip ◽  
Output Driver ◽  
Wide Operating ◽  
28 Nm

This paper presents a fully integrated Peripheral Component Interconnect (PCI) Express (PCIe) Gen4 physical layer (PHY) transmitter. The prototype chip is fabricated in a 28 nm low-power CMOS process, and the active area of the proposed transmitter is 0.23 mm2. To enable voltage scaling across wide operating rates from 2.5 Gb/s to 16 Gb/s, two on-chip supply regulators are included in the transmitter. At the same time, the regulators maintain the output impedance of the transmitter to meet the return loss specification of the PCIe, by including replica segments of the output driver and reference resistance in the regulator loop. A three-tap finite-impulse-response (FIR) equalization is implemented and, therefore, the transmitter provides more than 9.5 dB equalization which is required in the PCIe specification. At 16 Gb/s, the prototype chip achieves energy efficiency of 1.93 pJ/bit including all the interface, bias, and built-in self-test circuits.

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