scholarly journals A 1.93-pJ/Bit PCI Express Gen4 PHY Transmitter with On-Chip Supply Regulators in 28 nm CMOS

Electronics ◽  
2021 ◽  
Vol 10 (1) ◽  
pp. 68
Author(s):  
Woorham Bae ◽  
Sung-Yong Cho ◽  
Deog-Kyoon Jeong
Keyword(s):  
Finite Impulse Response ◽  
Cmos Process ◽  
Pci Express ◽  
Fully Integrated ◽  
Peripheral Component Interconnect ◽  
Low Power Cmos ◽  
On Chip ◽  
Output Driver ◽  
Wide Operating ◽  
28 Nm

This paper presents a fully integrated Peripheral Component Interconnect (PCI) Express (PCIe) Gen4 physical layer (PHY) transmitter. The prototype chip is fabricated in a 28 nm low-power CMOS process, and the active area of the proposed transmitter is 0.23 mm2. To enable voltage scaling across wide operating rates from 2.5 Gb/s to 16 Gb/s, two on-chip supply regulators are included in the transmitter. At the same time, the regulators maintain the output impedance of the transmitter to meet the return loss specification of the PCIe, by including replica segments of the output driver and reference resistance in the regulator loop. A three-tap finite-impulse-response (FIR) equalization is implemented and, therefore, the transmitter provides more than 9.5 dB equalization which is required in the PCIe specification. At 16 Gb/s, the prototype chip achieves energy efficiency of 1.93 pJ/bit including all the interface, bias, and built-in self-test circuits.

scholarly journals A 1.55-to-32-Gb/s Four-Lane Transmitter with 3-Tap Feed Forward Equalizer and Shared PLL in 28-nm CMOS

Electronics ◽  
2021 ◽  
Vol 10 (16) ◽  
pp. 1873
Author(s):  
Chen Cai ◽  
Xuqiang Zheng ◽  
Yong Chen ◽  
Danyu Wu ◽  
Jian Luan ◽  
...  
Keyword(s):  
Data Transmission ◽  
High Speed ◽  
Data Rate ◽  
Quality Data ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Feed Forward ◽  
Fully Integrated ◽  
Output Driver ◽  
28 Nm

This paper presents a fully integrated physical layer (PHY) transmitter (TX) suiting for multiple industrial protocols and compatible with different protocol versions. Targeting a wide operating range, the LC-based phase-locked loop (PLL) with a dual voltage-controlled oscillator (VCO) was integrated to provide the low jitter clock. Each lane with a configurable serialization scheme was adapted to adjust the data rate flexibly. To achieve high-speed data transmission, several bandwidth-extended techniques were introduced, and an optimized output driver with a 3-tap feed-forward equalizer (FFE) was proposed to accomplish high-quality data transmission and equalization. The TX prototype was fabricated in a 28-nm CMOS process, and a single-lane TX only occupied an active area of 0.048 mm2. The shared PLL and clock distribution circuits occupied an area of 0.54 mm2. The proposed PLL can support a tuning range that covers 6.2 to 16 GHz. Each lane's data rate ranged from 1.55 to 32 Gb/s, and the energy efficiency is 1.89 pJ/bit/lane at a 32-Gb/s data rate and can tune an equalization up to 10 dB.

scholarly journals A Fully Integrated Compact Outphasing CMOS Power Amplifier Using a Parallel-Combining Transformer with a Tuning Inductor Method

Electronics ◽  
2020 ◽  
Vol 9 (2) ◽  
pp. 257 ◽  
Author(s):  
Se-Eun Choi ◽  
Hyunjin Ahn ◽  
Joonhoi Hur ◽  
Kwan-Woo Kim ◽  
Ilku Nam ◽  
...  
Keyword(s):  
Output Power ◽  
Power Amplifier ◽  
Cmos Process ◽  
Power Combining ◽  
Fully Integrated ◽  
Term Evolution ◽  
Class D ◽  
Adjacent Channel ◽  
On Chip

This work presents a compact on-chip outphasing power amplifier with a parallel-combining transformer (PCT). A series-combining transformer (SCT) and PCT are analyzed as power-combining transformers for outphasing operations. Compared to the SCT, which is typically used for on-chip outphasing combiners, the PCT is much smaller. The outphasing operations of the transformer combiners and class-D switching PAs are also analyzed. A tuning inductor method is proposed to improve the efficiency of class-D power amplifiers (PAs) with power-combining transformers in the out-of-phase mode. The proposed PA was implemented with a standard 0.18 µm CMOS process. The measured maximum drain efficiency is 37.3% with an output power of 22.4 dBm at 1.7 GHz. A measured adjacent channel leakage ratio (ACLR) of less than −30 dBc is obtained for a long-term evolution (LTE) signal with a bandwidth of 10 MHz.

An ESD Protected Wideband CMOS Low Noise Amplifier Employing Active Feedback Technique

2011 ◽  
Vol 403-408 ◽  
pp. 2809-2813
Author(s):  
Kuan Bao ◽  
Xiang Ning Fan
Keyword(s):  
Noise Figure ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Cmos Process ◽  
Fully Integrated ◽  
Input Matching ◽  
Active Feedback ◽  
Cmos Lna ◽  
Noise Amplifier ◽  
On Chip

This paper presents a wideband low noise amplifier (LNA) for multi-standard radio applications. The low noise characteristic and input matching are simultaneously achieved by active-feedback technique. Bond-wire inductors and electrostatic devices (ESDs) are co-designed to improve the chip performance. Implemented in 0.18-μm CMOS process, the core size of the fully integrated LNA circuits is 535 μm×425 μm without any passive on-chip inductor. The simulated gain and the minimal noise figure of the CMOS LNA are 17.5 dB and 2.0 dB, respectively. The LNA achieves a -3dB bandwidth of 3.1 GHz. And the simulated IIP3 is -4.4 dBm at 2.5 GHz. Operating at 1.8V, the LNA draws a current of 7.7 mA.

A 975-mW Fully Integrated Genetic Variant Discovery System-on-Chip in 28 nm for Next-Generation Sequencing

2021 ◽  
Vol 56 (1) ◽  
pp. 123-135
Author(s):  
Yi-Chung Wu ◽  
Yen-Lung Chen ◽  
Chung-Hsuan Yang ◽  
Chao-Hsi Lee ◽  
Chao-Yang Yu ◽  
...  
Keyword(s):  
Next Generation Sequencing ◽  
Genetic Variant ◽  
System On Chip ◽  
Next Generation ◽  
Fully Integrated ◽  
Variant Discovery ◽  
Discovery System ◽  
On Chip ◽  
Generation Sequencing ◽  
28 Nm

A 120GHz fully integrated 10Gb/s wireless transmitter with on-chip antenna in 45nm low power CMOS

2013 ◽  
Author(s):  
Noel Deferm ◽  
Wouter Volkaerts ◽  
Juan F. Osorio ◽  
Anton de Graauw ◽  
Michiel Steyaert ◽  
...  
Keyword(s):  
Low Power ◽  
Fully Integrated ◽  
Wireless Transmitter ◽  
On Chip Antenna ◽  
Low Power Cmos ◽  
On Chip

scholarly journals A system-on-chip 1.5 GHz phase locked loop realized using 40 nm CMOS technology

2018 ◽  
Vol 31 (1) ◽  
pp. 101-113
Author(s):  
Weiyin Wang ◽  
Xiangjie Chen ◽  
Hei Wong
Keyword(s):  
Cmos Technology ◽  
System On Chip ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Sigma Delta ◽  
Fully Integrated ◽  
Measurement Results ◽  
Feedback Structure ◽  
On Chip ◽  
Frequency Detector

This work presents the design and realization of a fully-integrated 1.5 GHz sigma-delta fractional-N ring-based PLL for system-on-chip (SoC) applications. Some design optimizations were conducted to improve the performance of each functional block such as phase frequency detector (PFD), voltage-controlled oscillator (VCO), filter and charge pump (CP) and so as for the whole system. In particular, a time delay circuit is designed for overcoming the blind zone in the PFD; an operational amplifier-feedback structure was used to eliminate the current mismatch in the CP, a 3rd LPF is used for suppressing noises and a current overdrive structure is used in VCO design. The design was realized with a commercial 40 nm CMOS process. The core die sized about 0.041 mm2. Measurement results indicated that the circuit functions well for the locked range between 500 MHz to 1.5 GHz.

scholarly journals A Fully Integrated Clocked AC-DC Charge Pump for Mignetostrictive Vibration Energy Harvesting

Electronics ◽  
2020 ◽  
Vol 9 (12) ◽  
pp. 2194
Author(s):  
Hayato Kawauchi ◽  
Toru Tanzawa
Keyword(s):  
Output Power ◽  
Charge Pump ◽  
Input Voltage ◽  
Open Circuit ◽  
Vibration Energy ◽  
Cmos Process ◽  
Vibration Energy Harvesting ◽  
Fully Integrated ◽  
Energy Transducer ◽  
On Chip

This paper describes a clocked AC-DC charge pump to enable full integration of power converters into a sensor or radio frequency (RF) chip even with low open circuit voltage magnetostrictive vibration energy transducer operating at a low resonant frequency of 10 Hz to 1 kHz. The frequency of the clock to drive an AC-DC charge pump was up-converted with an on-chip oscillator to increase output power of the charge pump without significantly increasing the circuit area. A model of the system including the charge pump and vibration energy transducer is shown. It was validated by HSPICE simulation and measured, resulting in a prototype chip with an area of 0.11 mm2 fabricated in a 65 nm 1 V CMOS process. The fabricated charge pump was also measured together with a magnetostrictive transducer. The charge pump converted the power from the transducer to an output power of 4.2 μW at an output voltage of 2.0 V. The output power varied below 3% over a wide input frequency of 10 Hz to 100 kHz, which suggests that universal design of the clocked AC-DC charge pump can be used for transducers with different resonant frequencies. In a low-input voltage region below 0.8 V, the proposed circuit has higher output power compared with the conventional circuits.

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