A 25 Gbps VCSEL driving ASIC: an attempt for ultra-high-speed front-end readout applications

This paper presents the design and the test results of a 25 Gbps VCSEL driving ASIC fabricated in a 55 nm CMOS technology as an attempt for the future very high-speed optical links. The VCSEL driving ASIC is composed of an input equalizer stage, a pre-driver stage and a novel output driver stage. To achieve high bandwidth, the pre-driver stage combines the inductor-shared peaking structure and the active-feedback technique. A novel output driver stage uses the pseudo differential CML driver structure and the adjustable FFE pre-emphasis technique to improve the bandwidth. This VCSEL driver has been integrated in a customized optical module with a VCSEL array. Both the electrical function and optical performance have been fully evaluated. The output optical eye diagram has passed the eye mask test at the data rate of 25 Gbps. The peak-to-peak jitter of 25 Gbps optical eye is 19.5 ps and the RMS jitter is 2.9 ps.

LDLA14: a 14 Gbps optical transceiver ASIC in 55 nm for NICA multi purpose detector project

This paper presents the design and test results of a 14 Gbps optical transceiver ASIC (LDLA14) fabricated in a 55 nm CMOS technology for NICA Multi Purpose Detector (MPD) project. The LDLA14 is a single-channel bidirectional (1Tx + 1Rx) optical transceiver ASIC, including a Laser Driver (LD) module and a Limiting Amplifier (LA) module. It would drive the Vertical Cavity Surface Emitting Laser (VCSEL) of Transmitter Optical Sub-Assembly (TOSA) and receive signals from Photo Diode (PD) of Receiver Optical Sub-Assembly (ROSA), respectively. In the LDLA14, a novel structure of capacitive coupling pre-emphasis is proposed in the output driver of LD to obtain peaking effect without sacrifice the modulation current swing. A shared inductor technology and a Continuous Time Linear Equalizer (CTLE) pre-emphasis structure are added in the output buffer of LA to improve the quality of the output eye diagram. The dimension of LDLA14 is 1.5 mm × 1.3 mm, and the power consumption is 178 mW. The Peak-to-Peak Jitter (PPJ) and Root-Mean-Square Jitter (RMSJ) of the 14 Gbps optical eye diagram of LD in the Tx direction are 22.5 ps and 3.5 ps, respectively. The PPJ and RMSJ of the 14 Gbps electrical eye diagram of LA in the Rx direction are 23.1 ps and 4.7 ps, respectively. The BER tests have been conducted in Tx, Rx directions and the Tx-Rx loop condition, and the BER less than 10−12 is achieved in all tests.

A 1.55-to-32-Gb/s Four-Lane Transmitter with 3-Tap Feed Forward Equalizer and Shared PLL in 28-nm CMOS

This paper presents a fully integrated physical layer (PHY) transmitter (TX) suiting for multiple industrial protocols and compatible with different protocol versions. Targeting a wide operating range, the LC-based phase-locked loop (PLL) with a dual voltage-controlled oscillator (VCO) was integrated to provide the low jitter clock. Each lane with a configurable serialization scheme was adapted to adjust the data rate flexibly. To achieve high-speed data transmission, several bandwidth-extended techniques were introduced, and an optimized output driver with a 3-tap feed-forward equalizer (FFE) was proposed to accomplish high-quality data transmission and equalization. The TX prototype was fabricated in a 28-nm CMOS process, and a single-lane TX only occupied an active area of 0.048 mm2. The shared PLL and clock distribution circuits occupied an area of 0.54 mm2. The proposed PLL can support a tuning range that covers 6.2 to 16 GHz. Each lane's data rate ranged from 1.55 to 32 Gb/s, and the energy efficiency is 1.89 pJ/bit/lane at a 32-Gb/s data rate and can tune an equalization up to 10 dB.

An 18-Gb/s/pin Single-Ended PAM-4 Transmitter for Memory Interfaces with Adaptive Impedance Matching and Output Level Compensation

This paper presents a method for preventing output level distortion while matching the channel impedance in the single-ended PAM-4 transmitter for memory interfaces. ZQ codes for all four output signal levels were obtained through ZQ calibration and saved in the ZQ code table. The ZQ code generator then adaptively selected the appropriate codes depending on the data pattern and delivered them to the output driver; this can improve the level separation mismatch ratio (RLM) while matching the channel impedance. To validate the effectiveness of our approach, a prototype chip with an active area of 0.035 mm2 was fabricated in a 65 nm CMOS process. It achieved the energy efficiency of 3.09 pJ/bit/pin at 18 Gb/s/pin, and its RLM was 0.971 while matching the channel impedance.

On Small Scale LNG Concepts

The different economics of small scale LNG plants put more emphasis on capital expenses over process efficiency, and thus favors simpler refrigeration cycles. We typically find reverse Brayton cycles, or SMR (Single mixed refrigerant) cycles. These cycles have specific requirements to the compression equipment, and typically have smaller drivers, either electric drives or gas turbines. The relationship between output, driver size, and process preferences is explained. The type of compressors, and expanders needed are discussed, together with thoughts and the driver preferences. This includes the different control methods that can be used, both for the cycle adaptation, as well as the related control of the compressors, expanders, valves and drivers. Equipment performance maps are created to highlight the required different operating conditions. This result allows for subsequent optimization discussions.

Multiple Use SiPM Integrated Circuit (MUSIC) for Large Area and High Performance Sensors

The 8-channel Multiple Use Silicon Photo-multiplier (SiPM) Integrated Circuit (MUSIC) Application specific integrated circuit (ASIC) for SiPM anode readout has been designed for applications where large photo-detection areas are required. MUSIC offers three main features: (1) Sum of the eight input channels using a differential output driver, (2) eight individual single ended (SE) analog outputs, and (3) eight individual SE binary outputs using a time over threshold technique. Each functionality, summation and individual readout includes a selectable dual-gain configuration. Moreover, the signal sum implements a dual-gain output providing a 15-bit dynamic range. The circuit contains a tunable pole zero cancellation of the SiPM recovery time constant to deal with most of the available SiPM devices in the market. Experimental tests show how MUSIC can linearly sum signals from different SiPMs and distinguish even a few photons. Additionally, it provides a single photon output pulse width at half maximum (FWHM) between 5–10 ns for the analog output and a single-photon time resolution (SPTR) around 118 ps sigma using a Hamamatsu SiPM S13360-3075CS for the binary output. Lastly, the summation mode has a power consumption of ≈200 mW, whereas the individual readout consumes ≈30 mW/ch.

A 1.93-pJ/Bit PCI Express Gen4 PHY Transmitter with On-Chip Supply Regulators in 28 nm CMOS

This paper presents a fully integrated Peripheral Component Interconnect (PCI) Express (PCIe) Gen4 physical layer (PHY) transmitter. The prototype chip is fabricated in a 28 nm low-power CMOS process, and the active area of the proposed transmitter is 0.23 mm2. To enable voltage scaling across wide operating rates from 2.5 Gb/s to 16 Gb/s, two on-chip supply regulators are included in the transmitter. At the same time, the regulators maintain the output impedance of the transmitter to meet the return loss specification of the PCIe, by including replica segments of the output driver and reference resistance in the regulator loop. A three-tap finite-impulse-response (FIR) equalization is implemented and, therefore, the transmitter provides more than 9.5 dB equalization which is required in the PCIe specification. At 16 Gb/s, the prototype chip achieves energy efficiency of 1.93 pJ/bit including all the interface, bias, and built-in self-test circuits.

CMOS Based Ovonic Threshold Switching Emulation Circuitry

Ovonic Threshold Switch (OTS) device is most popular switching device in PRAM. There are many OTS device research; however, it is hard to make reasonable OTS device which uses a circuit simulation and real device. In this work, we studied the OTS device emulation circuit, which can follow OTS characteristic, especially snapback current using 0.18 μm CMOS technology. This circuitry composes snapback current generator, cut off switch and output driver. Snapback current generator can make the current level up to 300 μA.

A Generic Test Board for the Electrical Characterization of ULP and ULV Fully-Differential Integrated Analog Circuits

The characterization of ultra-low power (ULP) fully-differential/balanced amplifiers and active filters is challenging due to the incompatibility with the classical single-ended (SE) and 50 Ω impedance equipment. Interface circuits between the device under test (DUT) and the equipment are needed to perform the signal conversion and to work as voltage buffers. In this work, we propose a generic test circuits to be used in the characterization of ULP and ultra-low voltage (ULV) analog circuits. The test board includes balun transformers to the signal conversion, a high input impedance and low capacitance output driver and voltage regulators to provide the target DUT supply voltage. The characterization of the proposed PCB demonstrates a bandwidth of 30 MHz, output driver input impedance of 5 MΩ with 2.5 pF capacitance and low input-referred noise. The proposed circuit was applied to the electrical characterization of two fully-differential ULV and ULP analog integrated circuits.