Design of Fault Tolerant Single RAM-Based Parallel Real Fast Fourier Transform Architectures Using Error Correction Codes and Parseval Checks

Abstract In this work, we develop the theory of quasi-exact fault-tolerant quantum (QEQ) computation, which uses qubits encoded into quasi-exact quantum error-correction codes (``quasi codes''). By definition, a quasi code is a parametric approximate code that can become exact by tuning its parameters. The model of QEQ computation lies in between the two well-known ones: the usual noisy quantum computation without error correction and the usual fault-tolerant quantum computation, but closer to the later. Many notions of exact quantum codes need to be adjusted for the quasi setting. Here we develop quasi error-correction theory using quantum instrument, the notions of quasi universality, quasi code distances, and quasi thresholds, etc. We find a wide class of quasi codes which are called valence-bond-solid codes, and we use them as concrete examples to demonstrate QEQ computation.

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Fault Tolerant Parallel Filters Based on Error Correction Codes

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2014.2308322 ◽

2015 ◽

Vol 23 (2) ◽

pp. 384-387 ◽

Cited By ~ 12

Author(s):

Zhen Gao ◽

Pedro Reviriego ◽

Wen Pan ◽

Zhan Xu ◽

Ming Zhao ◽

...

Keyword(s):

Error Correction ◽

Fault Tolerant ◽

Error Correction Codes

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Analysis of Open-Circuit Fault in Fault-Tolerant BLDC Motors with Different Winding Configurations

Energies ◽

10.3390/en13205321 ◽

2020 ◽

Vol 13 (20) ◽

pp. 5321

Author(s):

Mariusz Korkosz ◽

Jan Prokop ◽

Bartlomiej Pakla ◽

Grzegorz Podskarbi ◽

Piotr Bogusz

Keyword(s):

Mathematical Model ◽

Fourier Transform ◽

Fast Fourier Transform ◽

Permanent Magnet ◽

Fault Tolerant ◽

Open Circuit ◽

Numerical Calculations ◽

Star Configuration ◽

Permanent Magnet Dc Motor ◽

Fft Analysis

In this study, tests were carried out on a brushless permanent magnet DC motor with different winding configurations. Three configurations were compared: star, delta and combined star–delta. A mathematical model was constructed for the motor, taking into account the different winding configurations. An analysis of the operation of the motor in the different configurations was performed, based on numerical calculations. The use of different winding configurations affects the properties of the motor. This is significant in the case of the occurrence of various fault states. Based on numerical calculations, an analysis of an open-circuit fault in one of the phases of the motor was performed. Fast Fourier Transform—FFT analysis of the artificial neutral-point voltage was used for the detection of fault states. The results were verified by tests carried out under laboratory conditions. It was shown that the winding configuration has an impact on the behaviour of the motor in the case of an open circuit in one of the phases. The classical star configuration is the worst of the possible arrangements. The most favourable in this respect is the delta configuration. In the case of the combined star–delta configuration, the consequences of the fault depend on the location of the open circuit.

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Design of low- area, power fault tolerant parallel FFTs using trellis codes

International Journal of Engineering & Technology ◽

10.14419/ijet.v7i4.14106 ◽

2018 ◽

Vol 7 (4) ◽

pp. 2338

Author(s):

B. NagaSaiLakshmi ◽

RajaSekhar. T

Keyword(s):

Error Correction ◽

Fault Tolerant ◽

Error Correction Codes ◽

Electronic Circuits ◽

Trellis Codes ◽

Low Area ◽

Trellis Code ◽

Synthesis Report ◽

Parallel Fft ◽

Algorithmic Based Fault Tolerance

Present day electronic circuits are generally affected by the delicate mistakes. To maintain the reliability of the complex systems few techniques have been proposed. For few applications, an algorithmic - based fault tolerance (ABFT) system has attempt to abuse the algorithmic properties to identify and adjust mistakes. One example FFT used. There are various protection schemes to identify and adjust errors in FFTs. It is normal to discover various blocks are working in parallel. Recently; a new method is exploiting to implement a blame tolerance in parallel. In this work, same method is first applicable to parallel FFT and then secured methods are merged that the use of error correction codes (ECCs) and parseval checks are used to detect and correct a single bit fault. Trellis code is applied to parallel FFTs to protect the errors which are used to detect and correct a multibit faults are proposed and evaluated. The 4-point FFT is protected with the input32-bit length .Simulation and Synthesis report for FFT using ECC,SOS,ECC-SOS,Trellis codes are obtained in Xilinx software14.2v.Area,power,delay is analyzed in cadence using 90nm & 180nmTechnology.

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