Fault tolerant encoders for Single Error Correction and Double Adjacent Error Correction codes

2018 ◽  
Vol 81 ◽  
pp. 167-173 ◽  
Author(s):  
Shanshan Liu ◽  
Pedro Reviriego ◽  
Juan Antonio Maestro ◽  
Liyi Xiao
Keyword(s):  
Error Correction ◽  
Fault Tolerant ◽  
Error Correction Codes ◽  
Single Error

scholarly journals Theory of quasi-exact fault-tolerant quantum computing and valence-bond-solid codes

2021 ◽  
Author(s):  
Dongsheng Wang ◽  
Yunjiang Wang ◽  
Ningping Cao ◽  
Bei Zeng ◽  
Raymond Lafflamme
Keyword(s):  
Error Correction ◽  
Quantum Computation ◽  
Fault Tolerant ◽  
Valence Bond ◽  
Quantum Error Correction ◽  
Quantum Codes ◽  
Error Correction Codes ◽  
Exact Quantum ◽  
Valence Bond Solid ◽  
Quantum Error

Abstract In this work, we develop the theory of quasi-exact fault-tolerant quantum (QEQ) computation, which uses qubits encoded into quasi-exact quantum error-correction codes (``quasi codes''). By definition, a quasi code is a parametric approximate code that can become exact by tuning its parameters. The model of QEQ computation lies in between the two well-known ones: the usual noisy quantum computation without error correction and the usual fault-tolerant quantum computation, but closer to the later. Many notions of exact quantum codes need to be adjusted for the quasi setting. Here we develop quasi error-correction theory using quantum instrument, the notions of quasi universality, quasi code distances, and quasi thresholds, etc. We find a wide class of quasi codes which are called valence-bond-solid codes, and we use them as concrete examples to demonstrate QEQ computation.

Ultrafast Single Error Correction Codes for Protecting Processor Registers

2015 ◽  
Author(s):  
Luis-J. Saiz-Adalid ◽  
Pedro Gil ◽  
Joaquin Gracia-Moran ◽  
Daniel Gil-Tomas ◽  
J.-Carlos Baraza-Calvo
Keyword(s):  
Error Correction ◽  
Error Correction Codes ◽  
Single Error

Fault Tolerant Parallel Filters Based on Error Correction Codes

2015 ◽  
Vol 23 (2) ◽  
pp. 384-387 ◽  
Author(s):  
Zhen Gao ◽  
Pedro Reviriego ◽  
Wen Pan ◽  
Zhan Xu ◽  
Ming Zhao ◽  
...  
Keyword(s):  
Error Correction ◽  
Fault Tolerant ◽  
Error Correction Codes

A Method to Design Single Error Correction Codes With Fast Decoding for a Subset of Critical Bits

2016 ◽  
Vol 63 (2) ◽  
pp. 171-175 ◽  
Author(s):  
Pedro Reviriego ◽  
Mustafa Demirci ◽  
Adrian Evans ◽  
Juan Antonio Maestro
Keyword(s):  
Error Correction ◽  
Error Correction Codes ◽  
Single Error ◽  
Fast Decoding

Fault Tolerant Single Error Correction Encoders

2011 ◽  
Vol 27 (2) ◽  
pp. 215-218 ◽  
Author(s):  
Juan Antonio Maestro ◽  
Pedro Reviriego ◽  
Costas Argyrides ◽  
Dhiraj K. Pradhan
Keyword(s):  
Error Correction ◽  
Fault Tolerant ◽  
Single Error

scholarly journals Design of low- area, power fault tolerant parallel FFTs using trellis codes

2018 ◽  
Vol 7 (4) ◽  
pp. 2338
Author(s):  
B. NagaSaiLakshmi ◽  
RajaSekhar. T
Keyword(s):  
Error Correction ◽  
Fault Tolerant ◽  
Error Correction Codes ◽  
Electronic Circuits ◽  
Trellis Codes ◽  
Low Area ◽  
Trellis Code ◽  
Synthesis Report ◽  
Parallel Fft ◽  
Algorithmic Based Fault Tolerance

Present day electronic circuits are generally affected by the delicate mistakes. To maintain the reliability of the complex systems few techniques have been proposed. For few applications, an algorithmic - based fault tolerance (ABFT) system has attempt to abuse the algorithmic properties to identify and adjust mistakes. One example FFT used. There are various protection schemes to identify and adjust errors in FFTs. It is normal to discover various blocks are working in parallel. Recently; a new method is exploiting to implement a blame tolerance in parallel. In this work, same method is first applicable to parallel FFT and then secured methods are merged that the use of error correction codes (ECCs) and parseval checks are used to detect and correct a single bit fault. Trellis code is applied to parallel FFTs to protect the errors which are used to detect and correct a multibit faults are proposed and evaluated. The 4-point FFT is protected with the input32-bit length .Simulation and Synthesis report for FFT using ECC,SOS,ECC-SOS,Trellis codes are obtained in Xilinx software14.2v.Area,power,delay is analyzed in cadence using 90nm & 180nmTechnology. 

scholarly journals A Method to Construct Low Delay Single Error Correction Codes for Protecting Data Bits Only

2013 ◽  
Vol 32 (3) ◽  
pp. 479-483 ◽  
Author(s):  
Pedro Reviriego ◽  
Salvatore Pontarelli ◽  
Juan Antonio Maestro ◽  
Marco Ottavi
Keyword(s):  
Error Correction ◽  
Error Correction Codes ◽  
Low Delay ◽  
Single Error
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