Test power is the major issue for current generation
VLSI testing. It has become the biggest concern for today's SoC.
While reducing the design efforts, the modular design approach
in SoC (i.e., use of IP cores in SoC) has further exaggerated
the test power issue. It is not easy to select an effective low-power testing strategy from a large pool of diverse available
techniques. To find the proper solutions for test power reduction
strategy for IP core-based SoC, in this paper, starting
from the terminology and models for power consumption during
test, the state of the art in low-power testing is presented. The
paper contains the detailed survey on various power reduction
techniques proposed for all aspects of testing like external testing,
Built-In Self-Test techniques, and the advances in DFT techniques
emphasizing low power. Further, all the available low-power
testing techniques are strongly analyzed for their suitability to IP
core-based SoC.
Analysis of Leakage Power Reduction Techniques for Low Power VLSI Design