VLSI Design Flow Using Vinyas Design Bot

Author(s):  
Veena S. Chakravarthi ◽  
S. Sowndarya ◽  
Shubham Raj
Keyword(s):  
2021 ◽  
Vol 23 (05) ◽  
pp. 704-708
Author(s):  
Nischith T R ◽  
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Namita Palecha ◽  
John Alwyn ◽  
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...  

Grid weakness measurement is an extremely important process in the modern-day VLSI design flow. In designs that contain power gating switches, there are additional challenges. It is desirable to find the PG grid weakness of only the gated domain. The tools used in the industry typically measure the total voltage drops from the bump location to the transistor pin. This voltage drop is the summation of the voltage drops in the external domain, switch pin network, and internal domain. This paper explores the ways to measure the internal pin domain voltage exclusively. Ansys Totem tool is used for simulation. Finally, the simulation results are presented to propose the effectiveness and accuracy of the given solution.


2020 ◽  
Vol 96 (3s) ◽  
pp. 460-470
Author(s):  
Л.П. Плеханов ◽  
А.Н. Денисов ◽  
Ю.Г. Дьяченко ◽  
Ю.А. Степченков ◽  
Д.И. Мамонов ◽  
...  

Данный доклад посвящен разработке средств автоматизированного синтеза самосинхронных (CC) схем. Рассматриваются особенности реализации СС-схем. Предложен маршрут проектирования цифровых СС СБИС. Описана интеграция разрабатываемых средств в стандартную САПР синхронных СБИС («Ковчег»), обеспечивающая эффективное проектирование действительно СС-схем. This report is devoted to the development of software for automated synthesis of the self-timed (ST) circuits. Peculiarities of the ST circuit implementation have been discussed, and digital ST VLSI design flow has been offered. Besides, the report highlights an integration of the suggested tools into standard synchronous VLSI CAD (“Kovcheg”), which provides the effective design of real ST circuits.


2018 ◽  
Vol 7 (2.16) ◽  
pp. 94
Author(s):  
Kumara Swamy Varkuti ◽  
Prabhu Benakop

Information Communication Technology (ICT) and Information Security (IS) are playing vital role in the present day communications. Information is prone to side channel attacks at software level where as it is very difficult to hack the information at hardware level.  Security is the major concern in the paperless communication and cashless online transactions. This paper aims to implement the most secured Improved Modified Blowfish Algorithm (IMBFA) by incorporating cell substitution using Wave Dynamic Differential Logic (WDDL) and interconnect decomposition  in the VLSI Design flow to not to allow the hacker to estimate or predict the key. Proposed IMBFA which can result in high speed, high throughput and effective memory utilization compared to Data Encryption Standard (DES), Triple Data Encryption Standard (TDES), Advanced Encryption Standard (AES) and Blowfish (BF). In this research paper, IMBFA yielded minimum delay as 71.067 ns, frequency of the design as 14.07 MHz, memory utilization as 62.481MB and throughput is 900Mbps compared to AES, TDES and DES algorithms. It is simulated using ModelSim, Synthesized using Leonardo Spectrum and implemented using Verilog HDL. 


Author(s):  
A.O. Vlasov ◽  
A.A. Gorelov ◽  
E.K. Emin ◽  
◽  
◽  
...  
Keyword(s):  

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