Test generation, design-for-testability and built-in self-test for arithmetic units based on graph labeling

1991 ◽  
Vol 2 (4) ◽  
pp. 351-372 ◽  
Author(s):  
Abhijit Chatterjee ◽  
Jacob A. Abraham
Keyword(s):  
Test Generation ◽  
Design For Testability ◽  
Graph Labeling ◽  
Self Test ◽  
Arithmetic Units ◽  
Built In Self Test

Design for Testability of High-Speed Advance Multipliers

2020 ◽  
pp. 175-190
Author(s):  
Suman Lata Tripathi
Keyword(s):  
High Speed ◽  
High Performance ◽  
Design For Testability ◽  
Online Testing ◽  
Efficient Design ◽  
Self Test ◽  
Built In Self Test ◽  
Work Done ◽  
Testing Work ◽  
Circuit Under Test

An efficient design for testability (DFT) has been a major thrust of area for today's VLSI engineers. A poorly designed DFT would result in losses for manufacturers with a considerable rework for the designers. BIST (built-in self-test), one of the promising DFT techniques, is rapidly modifying with the advances in technology as the device shrinks. The increasing complexities of the hardware have shifted the trend to include BISTs in high performance circuitry for offline as well as online testing. Work done here involves testing a circuit under test (CUT) with built in response analyser and vector generator with a monitor to control all the activities.

scholarly journals Base band processor for IEEE 802.11a standard with embedded BIST

2004 ◽  
Vol 17 (2) ◽  
pp. 231-239 ◽  
Author(s):  
Milos Krstic ◽  
Koushik Maharatna ◽  
Alfonso Troya ◽  
Eckhard Grass ◽  
Ulrich Jagdhold
Keyword(s):  
Low Power ◽  
Power Estimation ◽  
Design For Testability ◽  
Detailed Structure ◽  
Ieee 802.11A ◽  
Power Base ◽  
Self Test ◽  
Built In Self Test ◽  
Base Band

In this paper results of an IEEE 802.11a compliant low-power base band processor implementation are presented. The detailed structure of the base band processor and its constituent blocks is given. A design for testability strategy based on Built-In Self-Test (BIST) is proposed. Finally, implementation results and power estimation are reported.

Efficient test generation for built-in self-test boundary-scan template

2002 ◽  
Author(s):  
P. Nagvajara ◽  
M.G. Karpovsky ◽  
L.B. Levitin
Keyword(s):  
Test Generation ◽  
Boundary Scan ◽  
Efficient Test ◽  
Self Test ◽  
Built In Self Test

Design for testability and built-in self test: a review

1989 ◽  
Vol 36 (2) ◽  
pp. 129-140 ◽  
Author(s):  
H.T. Nagle ◽  
S.C. Roy ◽  
C.F. Hawkins ◽  
M.G. McNamer ◽  
R.R. Fritzemeier
Keyword(s):  
Design For Testability ◽  
Self Test ◽  
Built In Self Test
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