Design for testability and built-in self-test of integrated circuits and systems: how these can add value to your products

2002 ◽  
Author(s):  
A. Ivanov
Keyword(s):  
Integrated Circuits ◽  
Design For Testability ◽  
Self Test ◽  
Built In Self Test

Design for Testability of High-Speed Advance Multipliers

2020 ◽  
pp. 175-190
Author(s):  
Suman Lata Tripathi
Keyword(s):  
High Speed ◽  
High Performance ◽  
Design For Testability ◽  
Online Testing ◽  
Efficient Design ◽  
Self Test ◽  
Built In Self Test ◽  
Work Done ◽  
Testing Work ◽  
Circuit Under Test

An efficient design for testability (DFT) has been a major thrust of area for today's VLSI engineers. A poorly designed DFT would result in losses for manufacturers with a considerable rework for the designers. BIST (built-in self-test), one of the promising DFT techniques, is rapidly modifying with the advances in technology as the device shrinks. The increasing complexities of the hardware have shifted the trend to include BISTs in high performance circuitry for offline as well as online testing. Work done here involves testing a circuit under test (CUT) with built in response analyser and vector generator with a monitor to control all the activities.

scholarly journals A Built-in Self-Test System for External DRAM

2020 ◽  
pp. 80-87
Author(s):  
Gor Abgaryan
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
High Efficiency ◽  
Random Access ◽  
Test System ◽  
Mass Storage ◽  
Access Memory ◽  
Yield And Quality ◽  
Self Test ◽  
Built In Self Test

In the fast-growing Integrated Circuits (IC) industry, memory is one of the few keys to have systems with improved and fast performance. Only one transistor and a capacitor are required for Dynamic Random-Access Memory (DRAM) bit. It is widely used for mass storage. Although the high-efficiency tests are performed to provide the reliability of the memories, maintaining acceptable yield and quality is still the most critical task. To perform a high-speed effective test of DRAM memories, a built-in self-test (BIST) mechanism is proposed.

scholarly journals Base band processor for IEEE 802.11a standard with embedded BIST

2004 ◽  
Vol 17 (2) ◽  
pp. 231-239 ◽  
Author(s):  
Milos Krstic ◽  
Koushik Maharatna ◽  
Alfonso Troya ◽  
Eckhard Grass ◽  
Ulrich Jagdhold
Keyword(s):  
Low Power ◽  
Power Estimation ◽  
Design For Testability ◽  
Detailed Structure ◽  
Ieee 802.11A ◽  
Power Base ◽  
Self Test ◽  
Built In Self Test ◽  
Base Band

In this paper results of an IEEE 802.11a compliant low-power base band processor implementation are presented. The detailed structure of the base band processor and its constituent blocks is given. A design for testability strategy based on Built-In Self-Test (BIST) is proposed. Finally, implementation results and power estimation are reported.

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