A novel field programmable gate array architecture for high speed arithmetic processing

1998 ◽  
pp. 386-390 ◽  
Author(s):  
N. L. Miller ◽  
S. F. Quigley
Keyword(s):  
Field Programmable Gate Array ◽  
High Speed ◽  
Array Architecture ◽  
Field Programmable ◽  
Gate Array

High Speed FPGA Based 128-bit Advance Encryption Standard (AES)

2021 ◽  
Vol 11 ◽  
Author(s):  
Ibrahem M. T. Hamidi ◽  
Farah S. H. Al-aassi
Keyword(s):  
High Throughput ◽  
Field Programmable Gate Array ◽  
High Speed ◽  
Design Tool ◽  
Advanced Encryption Standard ◽  
Clock Frequency ◽  
Advance Encryption Standard ◽  
Field Programmable ◽  
Internal Component ◽  
Gate Array

Aim: Achieve high throughput 128 bits FPGA based Advanced Encryption Standard. Background: Field Programmable Gate Array (FPGA) provides an efficient platform for design AES cryptography system. It provides the capability to control over each bit using HDL programming language such as VHDL and Verilog which results an output speed in Gbps rang. Objective: Use Field Programmable Gate Array (FPGA) to design high throughput 128 bits FPGA based Advanced Encryption Standard. Method: Pipelining technique has used to achieve maximum possible speed. The level of pipelining includes round pipelining and internal component pipelining where number of registers inserted in particular places to increase the output speed. The proposed design uses combinatorial logic to implement the byte substitution. The s-box implemented using composed field arithmetic with 7 stages of pipelining to reduce the combinatorial logic level. The presented model has implemented using VHDL in Xilinix ISETM 14.4 design tool. Result: The achieved results were 18.55 Gbps at a clock frequency of 144.96 MHz and area of 1568 Slices in Spartan3 xc3s1000 hardware. Conclusion: The results show that the proposed design reaches a high throughput with acceptable area usage compare with other designs in the literature.

scholarly journals Novel Binary Signed-Digit Addition Algorithm for FPGA Implementation

2019 ◽  
Vol 29 (09) ◽  
pp. 2050136
Author(s):  
Yuuki Tanaka ◽  
Yuuki Suzuki ◽  
Shugang Wei
Keyword(s):  
Field Programmable Gate Array ◽  
High Speed ◽  
Number System ◽  
Logic Circuit ◽  
Fpga Implementation ◽  
Number Representation ◽  
Representation System ◽  
Representation Systems ◽  
Field Programmable ◽  
Gate Array

Signed-digit (SD) number representation systems have been studied for high-speed arithmetic. One important property of the SD number system is the possibility of performing addition without long carry chain. However, many numbers of logic elements are required when the number representation system and such an adder are realized on a logic circuit. In this study, we propose a new adder on the binary SD number system. The proposed adder uses more circuit area than the conventional SD adders when those adders are realized on ASIC. However, the proposed adder uses 20% less number of logic elements than the conventional SD adder when those adders are realized on a field-programmable gate array (FPGA) which is made up of 4-input 1-output LUT such as Intel Cyclone IV FPGA.

Real-time field programmable gate array architecture for computer vision

2001 ◽  
Vol 10 (1) ◽  
pp. 289 ◽  
Author(s):  
Miguel Arias-Estrada
Keyword(s):  
Computer Vision ◽  
Real Time ◽  
Field Programmable Gate Array ◽  
Array Architecture ◽  
Field Programmable ◽  
Gate Array

A very-high-speed field-programmable gate array using metal-to-metal antifuse programmable elements

1992 ◽  
Vol 23 (7) ◽  
pp. 561-568 ◽  
Author(s):  
J. Birkner ◽  
A. Chan ◽  
H.T. Chua ◽  
A. Chao ◽  
K. Gordon ◽  
...  
Keyword(s):  
Field Programmable Gate Array ◽  
High Speed ◽  
Field Programmable ◽  
Gate Array ◽  
Very High

scholarly journals High-speed endless optical polarization stabilization using calibrated waveplates and field-programmable gate array-based digital controller

2008 ◽  
Vol 16 (23) ◽  
pp. 18984 ◽  
Author(s):  
Ariya Hidayat ◽  
Benjamin Koch ◽  
Hongbin Zhang ◽  
Vitali Mirvoda ◽  
Manfred Lichtinger ◽  
...  
Keyword(s):  
Field Programmable Gate Array ◽  
High Speed ◽  
Digital Controller ◽  
Optical Polarization ◽  
Field Programmable ◽  
Gate Array

High Speed Matrix Multiplication Implementation Using Field Programmable Gate Array

2014 ◽  
Vol 7 (2) ◽  
pp. 75-78 ◽  
Author(s):  
Shriyashi Jain ◽  
◽  
Neeraj Kumar ◽  
Jaikaran Singh ◽  
Mukesh Tiwari
Keyword(s):  
Field Programmable Gate Array ◽  
High Speed ◽  
Matrix Multiplication ◽  
Field Programmable ◽  
Gate Array

Silicon Nanowire Transistors for Implementing an Field Programmable Gate Array Architecture with Scan Chain

2010 ◽  
Vol 4 (3) ◽  
pp. 342-352 ◽  
Author(s):  
Ahmet Bindal ◽  
Tomoko Ogura ◽  
Nori Ogura ◽  
Sotoudeh Hamedi-Hagh
Keyword(s):  
Field Programmable Gate Array ◽  
Silicon Nanowire ◽  
Nanowire Transistors ◽  
Array Architecture ◽  
Field Programmable ◽  
Gate Array ◽  
Scan Chain

Multichannel High-Speed Fiber Bragg Grating Interrogation System Utilizing a Field Programmable Gate Array

2018 ◽  
Vol 2 (1) ◽  
pp. 1-4 ◽  
Author(s):  
Tatsuya Yamaguchi ◽  
Yukitaka Shinoda
Keyword(s):  
Fiber Bragg Grating ◽  
Field Programmable Gate Array ◽  
High Speed ◽  
Bragg Grating ◽  
Field Programmable ◽  
Gate Array
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