A very-high-speed field-programmable gate array using metal-to-metal antifuse programmable elements

Aim: Achieve high throughput 128 bits FPGA based Advanced Encryption Standard. Background: Field Programmable Gate Array (FPGA) provides an efficient platform for design AES cryptography system. It provides the capability to control over each bit using HDL programming language such as VHDL and Verilog which results an output speed in Gbps rang. Objective: Use Field Programmable Gate Array (FPGA) to design high throughput 128 bits FPGA based Advanced Encryption Standard. Method: Pipelining technique has used to achieve maximum possible speed. The level of pipelining includes round pipelining and internal component pipelining where number of registers inserted in particular places to increase the output speed. The proposed design uses combinatorial logic to implement the byte substitution. The s-box implemented using composed field arithmetic with 7 stages of pipelining to reduce the combinatorial logic level. The presented model has implemented using VHDL in Xilinix ISETM 14.4 design tool. Result: The achieved results were 18.55 Gbps at a clock frequency of 144.96 MHz and area of 1568 Slices in Spartan3 xc3s1000 hardware. Conclusion: The results show that the proposed design reaches a high throughput with acceptable area usage compare with other designs in the literature.

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Theory and implementation of a very high throughput true random number generator in field programmable gate array

Review of Scientific Instruments ◽

10.1063/1.4945564 ◽

2016 ◽

Vol 87 (4) ◽

pp. 044704 ◽

Cited By ~ 6

Author(s):

Yonggang Wang ◽

Cong Hui ◽

Chong Liu ◽

Chao Xu

Keyword(s):

High Throughput ◽

Field Programmable Gate Array ◽

Random Number ◽

Random Number Generator ◽

Number Generator ◽

True Random Number Generator ◽

Field Programmable ◽

Gate Array ◽

Very High

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SYNTHESIS AND FPGA–IMPLEMENTATION BASED NEURAL TECHNIQUE OF A NONLINEAR ADC MODEL

International Journal of Computing ◽

10.47839/ijc.4.1.321 ◽

2014 ◽

pp. 27-33

Author(s):

Mounir Bouhedda ◽

Mokhtar Attari

Keyword(s):

Integrated Circuit ◽

Field Programmable Gate Array ◽

High Speed ◽

Hardware Description Language ◽

Description Language ◽

Analog To Digital ◽

Field Programmable ◽

Hardware Description ◽

Nonlinear Analog ◽

Very High

The aim of this paper is to introduce a new architecture using Artificial Neural Networks (ANN) in designing a 6-bit nonlinear Analog to Digital Converter (ADC). A study was conducted to synthesise an optimal ANN in view to FPGA (Field Programmable Gate Array) implementation using Very High-speed Integrated Circuit Hardware Description Language (VHDL). Simulation and tests results are carried out to show the efficiency of the designed ANN.

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Log-Domain Arithmetic for High-Speed Fuzzy Control on a Field-Programmable Gate Array

Soft Computing: State of the Art Theory and Novel Applications - Studies in Fuzziness and Soft Computing ◽

10.1007/978-3-642-34922-5_19 ◽

2013 ◽

pp. 269-287 ◽

Cited By ~ 1

Author(s):

Ali Razib ◽

Scott Dick ◽

Vincent Gaudet

Keyword(s):

Fuzzy Control ◽

Field Programmable Gate Array ◽

High Speed ◽

Field Programmable ◽

Gate Array ◽

Log Domain

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Novel Binary Signed-Digit Addition Algorithm for FPGA Implementation

Journal of Circuits System and Computers ◽

10.1142/s0218126620501364 ◽

2019 ◽

Vol 29 (09) ◽

pp. 2050136

Author(s):

Yuuki Tanaka ◽

Yuuki Suzuki ◽

Shugang Wei

Keyword(s):

Field Programmable Gate Array ◽

High Speed ◽

Number System ◽

Logic Circuit ◽

Fpga Implementation ◽

Number Representation ◽

Representation System ◽

Representation Systems ◽

Field Programmable ◽

Gate Array

Signed-digit (SD) number representation systems have been studied for high-speed arithmetic. One important property of the SD number system is the possibility of performing addition without long carry chain. However, many numbers of logic elements are required when the number representation system and such an adder are realized on a logic circuit. In this study, we propose a new adder on the binary SD number system. The proposed adder uses more circuit area than the conventional SD adders when those adders are realized on ASIC. However, the proposed adder uses 20% less number of logic elements than the conventional SD adder when those adders are realized on a field-programmable gate array (FPGA) which is made up of 4-input 1-output LUT such as Intel Cyclone IV FPGA.

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