ONOFIC Pull-Up Approach in Domino Logic Circuits Using FinFET for Subthreshold Leakage Reduction

2018 ◽  
Vol 38 (6) ◽  
pp. 2564-2587
Author(s):  
Vijay Kumar Magraiya ◽  
Tarun Kumar Gupta
Keyword(s):  
Logic Circuits ◽  
Domino Logic ◽  
Leakage Reduction ◽  
Subthreshold Leakage

DOIND: a technique for leakage reduction in nanoscale domino logic circuits

2016 ◽  
Vol 37 (5) ◽  
pp. 055001 ◽  
Author(s):  
Ambika Prasad Shah ◽  
Vaibhav Neema ◽  
Shreeniwas Daulatabad
Keyword(s):  
Logic Circuits ◽  
Domino Logic ◽  
Leakage Reduction

Dual threshold voltage and sleep switch dual threshold voltage DOIND approach for leakage reduction in domino logic circuits

2017 ◽  
Vol 25 (5) ◽  
pp. 1639-1652 ◽  
Author(s):  
Ambika Prasad Shah ◽  
Vaibhav Neema ◽  
Shreeniwas Daulatabad ◽  
Praveen Singh
Keyword(s):  
Threshold Voltage ◽  
Logic Circuits ◽  
Domino Logic ◽  
Leakage Reduction ◽  
Dual Threshold Voltage

Subthreshold Leakage reduction Strategies for the Design of Low Power Sram

2013 ◽  
Vol 1 (4) ◽  
pp. 6-13
Author(s):  
Vanitha . ◽  
◽  
M. Parimaladevi ◽  
D. Sharmila ◽  
◽  
...  
Keyword(s):  
Low Power ◽  
Leakage Reduction ◽  
Reduction Strategies ◽  
Subthreshold Leakage

Performance evaluation of domino logic circuits for wide fan-in gates with FinFET

2018 ◽  
Vol 24 (8) ◽  
pp. 3341-3348 ◽  
Author(s):  
Ajay Kumar Dadoria ◽  
Kavita Khare ◽  
Uday Panwar ◽  
Anita Jain
Keyword(s):  
Performance Evaluation ◽  
Logic Circuits ◽  
Domino Logic
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