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Performance evaluation of domino logic circuits for wide fan-in gates with FinFET
Microsystem Technologies
◽
10.1007/s00542-017-3691-3
◽
2018
◽
Vol 24
(8)
◽
pp. 3341-3348
◽
Cited By ~ 4
Author(s):
Ajay Kumar Dadoria
◽
Kavita Khare
◽
Uday Panwar
◽
Anita Jain
Keyword(s):
Performance Evaluation
◽
Logic Circuits
◽
Domino Logic
Download Full-text
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A Novel Technique to improve Performance Evaluation of Domino Logic Circuits in CMOS and FinFET Technology
2nd International Conference on Data, Engineering and Applications (IDEA)
◽
10.1109/idea49133.2020.9170682
◽
2020
◽
Author(s):
Uday Panwar
◽
Anat Shrivastava
Keyword(s):
Performance Evaluation
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Logic Circuits
◽
Improve Performance
◽
Domino Logic
◽
Novel Technique
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ONOFIC Pull-Up Approach in Domino Logic Circuits Using FinFET for Subthreshold Leakage Reduction
Circuits Systems and Signal Processing
◽
10.1007/s00034-018-0980-8
◽
2018
◽
Vol 38
(6)
◽
pp. 2564-2587
Author(s):
Vijay Kumar Magraiya
◽
Tarun Kumar Gupta
Keyword(s):
Logic Circuits
◽
Domino Logic
◽
Leakage Reduction
◽
Subthreshold Leakage
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Analytical performance evaluation of molecular logic circuits
The 16th CSI International Symposium on Computer Architecture and Digital Systems (CADS 2012)
◽
10.1109/cads.2012.6316428
◽
2012
◽
Cited By ~ 3
Author(s):
Mehdi Ghasemi
◽
Mohammad Hossein Moaiyeri
◽
Keivan Navi
Keyword(s):
Performance Evaluation
◽
Logic Circuits
◽
Analytical Performance
◽
Molecular Logic
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Charge sharing fault detection for CMOS domino logic circuits
Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99)
◽
10.1109/dftvs.1999.802872
◽
2003
◽
Cited By ~ 8
Author(s):
C.H. Cheng
◽
S.C. Chang
◽
J.S. Wang
◽
W.B. Jone
Keyword(s):
Fault Detection
◽
Logic Circuits
◽
Charge Sharing
◽
Domino Logic
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A Technique for Designing Totally Self-Checking Domino Logic Circuits
Sixth International Symposium on Quality of Electronic Design (ISQED'05)
◽
10.1109/isqed.2005.14
◽
2005
◽
Author(s):
C.K. Tang
◽
P.K. Lala
◽
J.P. Parkerson
Keyword(s):
Logic Circuits
◽
Domino Logic
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Impact of NBTI on performance of domino logic circuits in nano-scale CMOS
Microelectronics Journal
◽
10.1016/j.mejo.2011.09.009
◽
2011
◽
Cited By ~ 2
Author(s):
M. Houshmand Kaffashian
◽
R. Lotfi
◽
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◽
H. Mahmoodi
Keyword(s):
Logic Circuits
◽
Domino Logic
◽
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High-κ/metal gate low power bulk technology - Performance evaluation of standard CMOS logic circuits, microprocessor critical path replicas, and SRAM for 45nm and beyond
2009 International Symposium on VLSI Technology, Systems, and Applications
◽
10.1109/vtsa.2009.5159305
◽
2009
◽
Author(s):
D.-G. Park
◽
K. Stein
◽
K. Schruefer
◽
Y. Lee
◽
J.-P. Han
◽
...
Keyword(s):
Performance Evaluation
◽
Low Power
◽
Critical Path
◽
Logic Circuits
◽
Metal Gate
◽
Bulk Technology
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Mixed-swing methodology for domino logic circuits
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)
◽
10.1109/cicc.2001.929729
◽
2002
◽
Author(s):
A. Rave
◽
L.R. Carley
Keyword(s):
Logic Circuits
◽
Domino Logic
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PVT variations aware low leakage DOIND approach for nanoscale domino logic circuits
2015 IEEE Power, Communication and Information Technology Conference (PCITC)
◽
10.1109/pcitc.2015.7438222
◽
2015
◽
Cited By ~ 2
Author(s):
Ambika Prasad Shah
◽
Vaibhav Neema
◽
Shreeniwas Daulatabad
Keyword(s):
Logic Circuits
◽
Domino Logic
◽
Low Leakage
◽
Pvt Variations
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A novel leakage reduction DOIND approach for nanoscale domino logic circuits
2015 Eighth International Conference on Contemporary Computing (IC3)
◽
10.1109/ic3.2015.7346720
◽
2015
◽
Author(s):
Ambika Prasad Shah
◽
Vaibhav Neema
◽
Shreeniwas Daulatabad
Keyword(s):
Logic Circuits
◽
Domino Logic
◽
Leakage Reduction
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