An MTCMOS Subthreshold-Leakage Reduction Algorithm

2020 2nd Novel Intelligent and Leading Emerging Sciences Conference (NILES) ◽

10.1109/niles50944.2020.9257933 ◽

2020 ◽

Author(s):

Sherif M. Sharroush

Keyword(s):

Reduction Algorithm ◽

Leakage Reduction ◽

Subthreshold Leakage

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Subthreshold Leakage reduction Strategies for the Design of Low Power Sram

i-manager s Journal on Circuits and Systems ◽

10.26634/jcir.1.4.2590 ◽

2013 ◽

Vol 1 (4) ◽

pp. 6-13

Author(s):

Vanitha . ◽

◽

M. Parimaladevi ◽

D. Sharmila ◽

◽

...

Keyword(s):

Low Power ◽

Leakage Reduction ◽

Reduction Strategies ◽

Subthreshold Leakage

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ONOFIC Pull-Up Approach in Domino Logic Circuits Using FinFET for Subthreshold Leakage Reduction

Circuits Systems and Signal Processing ◽

10.1007/s00034-018-0980-8 ◽

2018 ◽

Vol 38 (6) ◽

pp. 2564-2587

Author(s):

Vijay Kumar Magraiya ◽

Tarun Kumar Gupta

Keyword(s):

Logic Circuits ◽

Domino Logic ◽

Leakage Reduction ◽

Subthreshold Leakage

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Revisited Design of Short-pulse Power Gated Approach of Subthreshold Leakage Reduction Technique in Combinational Circuits

2018 IEEE International Conference on System, Computation, Automation and Networking (ICSCA) ◽

10.1109/icscan.2018.8541204 ◽

2018 ◽

Author(s):

G Amuthavalli ◽

R Gunasundari

Keyword(s):

Short Pulse ◽

Reduction Technique ◽

Pulse Power ◽

Combinational Circuits ◽

Leakage Reduction ◽

Subthreshold Leakage

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Quantitative Evaluation of State-Preserving Leakage Reduction Algorithm for L1 Data Caches

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1093/ietfec/e88-a.4.862 ◽

2005 ◽

Vol E88-A (4) ◽

pp. 862-868 ◽

Author(s):

R. KOMIYA

Keyword(s):

Quantitative Evaluation ◽

Reduction Algorithm ◽

Leakage Reduction ◽

L1 Data ◽

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Subthreshold leakage reduction: A comparative study of SCL and CMOS design

2009 IEEE International Symposium on Circuits and Systems ◽

10.1109/iscas.2009.5118322 ◽

2009 ◽

Author(s):

Armin Tajalli ◽

Yusuf Leblebici

Keyword(s):

Comparative Study ◽

Leakage Reduction ◽

Cmos Design ◽

Subthreshold Leakage

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A Dual-Threshold FPGA Routing Design for Subthreshold Leakage Reduction

2007 IEEE International Symposium on Circuits and Systems ◽

10.1109/iscas.2007.378652 ◽

2007 ◽

Author(s):

Rodrigo Jaramillo-Ramirez ◽

Mohab Anis

Keyword(s):

Leakage Reduction ◽

Routing Design ◽

Subthreshold Leakage

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Adaptive Subthreshold Leakage Reduction Through N/P Wells Reverse Biasing

Lecture Notes in Computer Science - Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation ◽

10.1007/978-3-540-30205-6_4 ◽

2004 ◽

pp. 16-16

Author(s):

Carlo Dallavalle

Keyword(s):

Leakage Reduction ◽

Subthreshold Leakage

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Simulation and optimization of FILOX vertical MOSFET for subthreshold leakage reduction

2014 International Conference on Informatics, Electronics & Vision (ICIEV) ◽

10.1109/iciev.2014.6850806 ◽

2014 ◽

Author(s):

Md Enamul Haque Talal ◽

Peter Ashburn

Keyword(s):

Simulation And Optimization ◽

Leakage Reduction ◽

Subthreshold Leakage

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Analysis of subthreshold leakage reduction in CMOS digital circuits

2007 50th Midwest Symposium on Circuits and Systems ◽

10.1109/mwscas.2007.4488809 ◽

2007 ◽

Author(s):

Boray S. Deepaksubramanyan ◽

Adrian Nunez

Keyword(s):

Digital Circuits ◽

Leakage Reduction ◽

Subthreshold Leakage

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Application of an attribute reduction algorithm based on discernibility matrix in PBNM

Future Communication Technology ◽

10.2495/icct130561 ◽

2014 ◽

Author(s):

Shuo Feng ◽

Haiying Chu ◽

Xuyang Wang ◽

Yuanka Liang ◽

Xianwei Shi ◽

...

Keyword(s):

Attribute Reduction ◽

Reduction Algorithm ◽

Discernibility Matrix

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