Current-mode design techniques in low-voltage 24-GHz RF CMOS receiver front-end

2008 ◽  
Vol 58 (3) ◽  
pp. 183-195 ◽  
Author(s):  
Chung-Yu Wu ◽  
Wen-Chieh Wang ◽  
Fadi R. Shahroury ◽  
Zue-Der Huang ◽  
Hao-Jie Zhan
Keyword(s):  
Low Voltage ◽  
Current Mode ◽  
Rf Cmos ◽  
Mode Design ◽  
Front End ◽  
Cmos Receiver ◽  
24 Ghz ◽  
Design Techniques

A Low-Voltage CMOS Current Mode Integrated Transmitter Front-end for 2.4-GHz Wireless Communications

Frequenz ◽  
2010 ◽  
Vol 64 (11-12) ◽  
Author(s):  
Qiuzhen Wan ◽  
Chunhua Wang
Keyword(s):  
Wireless Communications ◽  
Low Voltage ◽  
Current Mode ◽  
Front End

scholarly journals A 1.8-V operation RF CMOS Receiver Front-End for WLAN/MAN

2013 ◽  
Vol 6 (6) ◽  
pp. 219-230
Author(s):  
Mi-young Lee ◽  
Young-Hun Lee
Keyword(s):  
Rf Cmos ◽  
Front End ◽  
Cmos Receiver

Low-power 24 GHz CMOS receiver front-end using isolation enhancement technique for automatic radar systems

2012 ◽  
Vol 54 (6) ◽  
pp. 1471-1476 ◽  
Author(s):  
Yong-Chin Chen ◽  
Chiu Hsuan Wang ◽  
Yo-Sheng Lin
Keyword(s):  
Low Power ◽  
Enhancement Technique ◽  
Radar Systems ◽  
Front End ◽  
Cmos Receiver ◽  
24 Ghz

Common Gate Transformer Feedback LNA in a High IIP3 Current Mode RF CMOS Front-End

2006 ◽  
Author(s):  
Antonio Liscidini ◽  
Cesare Ghezzi ◽  
Emanuele Depaoli ◽  
Guido Albasini ◽  
Ivan Bietti ◽  
...  
Keyword(s):  
Current Mode ◽  
Rf Cmos ◽  
Front End ◽  
Common Gate ◽  
Transformer Feedback

A high conversion gain, low noise figure RF-CMOS receiver front-end IC for 2.4-GHz applications

2010 ◽  
Author(s):  
Mahyar Nirouei ◽  
Soheil Ziabakhsh ◽  
Hosein Alavi-Rad ◽  
Saman Ziabakhsh
Keyword(s):  
Noise Figure ◽  
Low Noise ◽  
High Conversion ◽  
Conversion Gain ◽  
Rf Cmos ◽  
Front End ◽  
Cmos Receiver

A LOW-POWER LOW-VOLTAGE 6-BIT 1.33 GS/s FULLY MCML ALL NMOS FLASH ADC WITHOUT A FRONT-END T/H

2013 ◽  
Vol 22 (08) ◽  
pp. 1350074 ◽  
Author(s):  
SARA NESHANI ◽  
SEYED JAVAD AZHARI
Keyword(s):  
Low Power ◽  
Power Efficiency ◽  
Low Voltage ◽  
Current Mode ◽  
Flash Adc ◽  
Analog To Digital ◽  
Current Mode Logic ◽  
Front End ◽  
Compact Size ◽  
Nmos Transistors

In this work, a 6-bit 1.33 GS/s flash analog-to-digital converter (ADC) is proposed. To noticeably save the power and area and greatly increase the speed, compactness and accuracy its complete structure is elaborately implemented in MOS Current Mode Logic (MCML) topology. The proposed ADC does not use a front-end track and hold (T/H) block either. Furthermore, a novel optimized resistance ratio averaging-interpolation scheme is applied to: (1) reduce the offset, nonlinearity, number of preamplifiers, area and the power (2) increase the accuracy and mismatch insensitivity (3) minimize the size of elements towards the more compact size, smaller area and higher speed for the ADC. To maximize all these achievements, most favorably, it is completely built by NMOS transistors realizing the ever desired unique NMCML (NMOS-MCML) structure. Using intermediate gray encoding and exponential gains by extra latches greatly removes the bubble/meta-stability error and increases both the speed and the accuracy. Utilizing a differential ladder and some other deliberate arrangements reduces the kickback noise and common mode interferences, minimizes the structure and facilitates fast recovery of overdrive signals. The proposed ADC is simulated by Hspice using 0.18 μm TSMC technology and shows; effective resolution band width (ERBW) larger than 903 MHz that is 1.36 times more than Nyquist frequency (fs/2), 35.17 dB/49.4 dB SNDR/SFDR, 5.53 bits ENOB (rather flat SNDR and ENOB from 50 MHz to 750 MHz), and the low power consumption of 37.77 mW from a 1.2 V supply. These results prove that applying so many effective and novel plans has obtained a unique all N-MCML flash ADC with power-efficiency of 0.61 pJ per conversion step. Both Monte Carlo and corner cases simulations in addition to temperature analysis are performed that prove both intra-die and inter-die robustness of the proposed structure.

A low voltage current mode CMOS integrated receiver front-end for GPS system

2009 ◽  
Vol 63 (1) ◽  
pp. 23-31 ◽  
Author(s):  
Wang-Chi Cheng ◽  
Cheong-Fat Chan ◽  
Kong-Pang Pun ◽  
Chiu-Sing Choy
Keyword(s):  
Low Voltage ◽  
Current Mode ◽  
Front End ◽  
Gps System ◽  
Integrated Receiver

A differential low-voltage high gain current-mode integrated RF receiver front-end

2011 ◽  
Vol 32 (2) ◽  
pp. 025009 ◽  
Author(s):  
Chunhua Wang ◽  
Minglin Ma ◽  
Jingru Sun ◽  
Sichun Du ◽  
Xiaorong Guo ◽  
...  
Keyword(s):  
Low Voltage ◽  
Current Mode ◽  
High Gain ◽  
Rf Receiver ◽  
Front End
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