A gm-boosted common-gate CMOS low-noise amplifier with high P1dB

2014 ◽  
Vol 80 (1) ◽  
pp. 33-37 ◽  
Author(s):  
Sanghyun Woo ◽  
Jin Shao ◽  
Hyoungsoo Kim
Keyword(s):  
Low Noise ◽  
Low Noise Amplifier ◽  
Common Gate ◽  
Noise Amplifier

scholarly journals Analysis and design of common-gate low-noise amplifier for wideband applications

2009 ◽  
Vol 37 (2) ◽  
pp. 257-281 ◽  
Author(s):  
Jouni Kaukovuori ◽  
Mikko Kaltiokallio ◽  
Jussi Ryynänen
Keyword(s):  
Low Noise ◽  
Low Noise Amplifier ◽  
Analysis And Design ◽  
Common Gate ◽  
Noise Amplifier

scholarly journals A 2.4 GHz low noise amplifier design at 130nm CMOS technology using common gate topology for WiFi / WiMAX application

2017 ◽  
Vol 7 (1.3) ◽  
pp. 69
Author(s):  
M. Ramana Reddy ◽  
N.S Murthy Sharma ◽  
P. Chandra Sekhar
Keyword(s):  
Noise Figure ◽  
Cmos Technology ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Low Power Consumption ◽  
Common Gate ◽  
Chip Size ◽  
Overall Performance ◽  
Amplifier Design ◽  
Noise Amplifier

The proposed work shows an innovative designing in TSMC 130nm CMOS technology. A 2.4 GHz common gate topology low noise amplifier (LNA) using an active inductor to attain the low power consumption and to get the small chip size in layout design. By using this Common gate topology achieves the noise figure of 4dB, Forward gain (S21) parameter of 14.7dB, and the small chip size of 0.26 mm, while 0.8mW power consuming from a 1.1V in 130nm CMOS gives the better noise figure and improved the overall performance.

A 2.4/5.2/5.8 GHz Triple-Band Common-Gate Cascode CMOS Low-Noise Amplifier

2016 ◽  
Vol 36 (9) ◽  
pp. 3477-3490 ◽  
Author(s):  
Chun-Chieh Chen ◽  
Yen-Chun Wang
Keyword(s):  
Low Noise ◽  
Low Noise Amplifier ◽  
Common Gate ◽  
Noise Amplifier ◽  
Triple Band

A 5–7 GHz current reuse and gm-boosted common gate low noise amplifier with LC based ESD protection in 32 nm CMOS

2016 ◽  
Vol 90 (3) ◽  
pp. 573-589 ◽  
Author(s):  
Sriharsha Ankathi ◽  
Sriramula Vignan ◽  
Srikanth Athukuri ◽  
Smrithi Mohan ◽  
Karthigha Balamurugan ◽  
...  
Keyword(s):  
Low Noise ◽  
Low Noise Amplifier ◽  
Current Reuse ◽  
Esd Protection ◽  
Common Gate ◽  
Noise Amplifier

A common gate low noise amplifier with high linearity over UHF RFID bands

2008 ◽  
Author(s):  
Hyoung-Hwan Roh ◽  
Kyoung-Tae Park ◽  
Ha-Ryong Oh ◽  
Yeung-Rak Seong ◽  
Jun-Seok Park ◽  
...  
Keyword(s):  
Low Noise ◽  
Low Noise Amplifier ◽  
Uhf Rfid ◽  
High Linearity ◽  
Common Gate ◽  
Noise Amplifier

A 3–5 GHz ultra wideband common-gate low noise amplifier

2012 ◽  
Author(s):  
Abolfazl Zokaei ◽  
Masih Afzali Boroujeni ◽  
Farhad Razaghian ◽  
Jafar Alvankarian ◽  
Masoud Dousti
Keyword(s):  
Low Noise ◽  
Low Noise Amplifier ◽  
Ultra Wideband ◽  
Common Gate ◽  
Noise Amplifier

A wideband CMOS single-ended low noise amplifier employing negative resistance technique

2018 ◽  
Vol 32 (06) ◽  
pp. 1850068 ◽  
Author(s):  
Benqing Guo ◽  
Hongpeng Chen ◽  
Xuebing Wang ◽  
Jun Chen ◽  
Yueyue Li ◽  
...  
Keyword(s):  
Power Dissipation ◽  
Noise Figure ◽  
Cmos Technology ◽  
Negative Resistance ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Common Gate ◽  
Noise Amplifier ◽  
Maximal Gain ◽  
Resistance Structure

A wideband common-gate CMOS low noise amplifier with negative resistance technique is proposed. A novel single-ended negative resistance structure is employed to improve gain and noise of the LNA. The inductor resonating is adopted at the input stage and load stage to meet wideband matching and compensate gain roll-off at higher frequencies. Implemented in a 0.18 [Formula: see text]m CMOS technology, the proposed LNA demonstrates in simulations a maximal gain of 16.4 dB across the 3 dB bandwidth of 0.2–3 GHz. The in-band noise figure of 3.4–4.7 dB is obtained while the IIP3 of 5.3–6.8 dBm and IIP2 of 12.5–17.2 dBm are post-simulated in the designed frequency band. The LNA core consumes a power dissipation of 3.8 mW under a 1.5 V power supply.

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