A novel online offset-cancellation mechanism in a low-power 6-bit 2GS/s flash-ADC

2018 ◽  
Vol 99 (2) ◽  
pp. 219-229 ◽  
Author(s):  
Abdollah Amini ◽  
Ali Baradaranrezaeii ◽  
Mina Hassanzadazar
Keyword(s):  
Low Power ◽  
Flash Adc ◽  
Offset Cancellation

An Improved Low-Offset and Low-Power Design of Comparator for Flash ADC

2014 ◽  
Vol 598 ◽  
pp. 365-370
Author(s):  
Shuo Zhang ◽  
Zong Min Wang ◽  
Liang Zhou
Keyword(s):  
Low Power ◽  
Low Power Design ◽  
Cmos Process ◽  
Total Current ◽  
Flash Adc ◽  
Analog To Digital ◽  
Offset Cancellation ◽  
Offset Voltage ◽  
Current Consumption ◽  
Low Offset

This paper presents an offset-cancellation and low power cascaded comparator with new technique for flash Analog-to-Digital Converters. The improved structure cancels both input and output offset voltage by the feedback from outputs to common inputs. The total current consumption is reduced sharply for a clock circle with 1:2 dutyratio. The improved comparator is implemented in 0.35μm CMOS process. The Spectre simulation results show that the offset voltage of the improved structure is 3.14996mV with σ = 2.0347mV,and total current consumption is 17.59μA, while the offset voltage and total current consumption of the primary one is -5.649mV with σ = 14.254mV and 57.18μA respectively.

A 6-bit 1.2-GS/s low-power flash-ADC in 0.13-/spl mu/m digital CMOS

2005 ◽  
Vol 40 (7) ◽  
pp. 1499-1505 ◽  
Author(s):  
C. Sandner ◽  
M. Clara ◽  
A. Santner ◽  
T. Hartig ◽  
F. Kuttner
Keyword(s):  
Low Power ◽  
Digital Cmos ◽  
Flash Adc

scholarly journals A 6-bit 2GS/s Low Power Flash ADC

2012 ◽  
Vol 4 (4) ◽  
pp. 369-371
Author(s):  
Jyun Syong Lai ◽  
Zhi Ming Lin
Keyword(s):  
Low Power ◽  
Flash Adc

A low power flash adc system with fast data compression asic for a balloon-borne experiment

2003 ◽  
Vol 50 (4) ◽  
pp. 1214-1219 ◽  
Author(s):  
N. Matsui ◽  
K. Anraku ◽  
M. Imori ◽  
S. Nakazawa ◽  
Y. Toki
Keyword(s):  
Low Power ◽  
Data Compression ◽  
Flash Adc
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