A large gain variable range, high linearity, lownoise, low DC offset VGAs used in BD system

In this paper, a large gain variable range, high linearity, low noise, low DC offset VGAs with a simple gain-dB variable circuit are introduced. In the VGAs chain, the last and the first VGAs employ Bipolar transistors, to improve the linearity and noise characteristics. And the middle three stages VGAs employ MOS transistors. The whole circuitry is designed in 0.35um BiCMOS process, including variable gain amplifiers (VGAs) , fixed gain amplifiers , gain control and DC offset cancellation parts. The automatic gain control loop (AGC) provides a process independent gain variable range of 60dB (including 50dB gain-dB-linearity variable range), with a 200us loop lock time, the VGAs provide a 73dB largest gain, the THD is less than 1% at a 1V(P-P) output level; the equivalent output integral noise is 0.011v/√hz@20MHz bandwidth. The whole area is 1173um*494 um, and the power is 7.1mA at 3.3V signal supply voltage.

Dynamic Offset Compensated Operational Amplifiers

The given work is devoted to designing and implementing different dynamic offset cancellation techniques for 50 nm technology CMOS operational amplifiers. The goal is to minimize or get rid of the effects of the offset voltage. Offset voltage exists in all differential amplifiers due to the fact that no pair of transistors can be fabricated with the same size, there is always a slight difference in their dimensions (length or width), this gives rise to an undesirable effect called offset, the value of offset voltage for cheap commercial amplifiers are in the range of 1 to 10 mV, de-spite the fact that this isn’t a significant value, due to the high gain of such amplifiers, this voltage is amplified by tens or hundreds of times, this results in clipping of the output signal and this further limits the amplifier’s maximum allowable input voltage within the given dynamic range, hence its of great importance to take this small voltage into consideration, low-offset amplifiers find applications in mixers, analog to digital converters, instrumentation devices, etc. In this thesis, by using two different techniques for removing offset voltage (chopping and auto-zeroing), five low offset operational amplifiers were designed. The implemented methods reduced the flicker noise by more than 457 times (from 9.4 nV/√Hz to 20 pV/√Hz) at 1 Hz. All the simulations were done using Cadence Virtuoso.

Dynamic Offset Compensated Operational Amplifiers

The given work is devoted to designing and implementing different dynamic offset cancellation techniques for 50 nm technology CMOS operational amplifiers. The goal is to minimize or get rid of the effects of the offset voltage. Offset voltage exists in all differential amplifiers due to the fact that no pair of transistors can be fabricated with the same size, there is always a slight difference in their dimensions (length or width), this gives rise to an undesirable effect called offset, the value of offset voltage for cheap commercial amplifiers are in the range of 1 to 10 mV, de-spite the fact that this isn’t a significant value, due to the high gain of such amplifiers, this voltage is amplified by tens or hundreds of times, this results in clipping of the output signal and this further limits the amplifier’s maximum allowable input voltage within the given dynamic range, hence its of great importance to take this small voltage into consideration, low-offset amplifiers find applications in mixers, analog to digital converters, instrumentation devices, etc. In this thesis, by using two different techniques for removing offset voltage (chopping and auto-zeroing), five low offset operational amplifiers were designed. The implemented methods reduced the flicker noise by more than 457 times (from 9.4 nV/√Hz to 20 pV/√Hz) at 1 Hz. All the simulations were done using Cadence Virtuoso.

A Low-Power CMOS Bandgap Voltage Reference for Supply Voltages Down to 0.5 V

A voltage reference is strictly required for sensor interfaces that need to perform nonratiometric data acquisition. In this work, a voltage reference capable of working with supply voltages down to 0.5 V is presented. The voltage reference was based on a classic CMOS bandgap core, properly modified to be compatible with low-threshold or zero-threshold MOSFETs. The advantages of the proposed circuit are illustrated with theoretical analysis and supported by numerical simulations. The core was combined with a recently proposed switched capacitor, inverter-like integrator implementing offset cancellation and low-frequency noise reduction techniques. Experimental results performed on a prototype designed and fabricated using a commercial 0.18 μm CMOS process are presented. The prototype produces a reference voltage of 220 mV with a temperature sensitivity of 45 ppm/°C across a 10–50 °C temperature range. The proposed voltage reference can be used to source currents up to 100 μA with a quiescent current consumption of only 630 nA.

A Bond-Wire Drift Offset Minimized Capacitance-to-Digital Interface for MEMS Accelerometer with Gain-Enhanced VCO-Based Quantization and Nested Digital Chopping Feedback Loops

This paper presents an output offset minimized capacitance-to-digital interface for a MEMS accelerometer. With a gain-enhanced voltage-controlled oscillator (VCO)-based quantization loop, the interface is able to output a digital signal with improved dynamic range. For optimizing the output offset caused by nonideal factors (e.g., the bond-wire drift), a nested digital chopping feedback loop is embedded in the VCO-based quantization loop. It enables the interface to minimize the output offset without digital filtering and digital-to-analog conversion. The proposed architecture is well suited for dynamic range and offset improvements with low cost. Fabricated with a 0.18 μm Global Foundry (GF) CMOS process, the interface offers a 78 dB dynamic range with 0.4% nonlinearity from a single 2 V supply. With the input referred offset up to 1.3 pF, the offset cancellation loop keeps the DC output offset within 40 mV. The power dissipation is 6.5 mW with a bandwidth of 4 kHz.