An Improved Low-Offset and Low-Power Design of Comparator for Flash ADC

A low offset and high speed preamplifier latch comparator is proposed for high-speed pipeline analog-to-digital converters (ADCs). In order to realize low offset, both offset cancellation techniques and kickback noise reduction techniques are adopted. Based on TSMC 0.18 μm 3.3 V CMOS process, Monte Carlo simulation shows that the comparator has a low offset voltage 1.1806 mV at 1 sigma at 125 MHz, with a power dissipation of 413.48 μW.

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A LOW OFFSET COMPARATOR FOR HIGH SPEED LOW POWER ADC

Journal of Circuits System and Computers ◽

10.1142/s0218126613500618 ◽

2013 ◽

Vol 22 (07) ◽

pp. 1350061 ◽

Cited By ~ 2

Author(s):

ZHANGMING ZHU ◽

WEITIE WANG ◽

YUHENG GUAN ◽

SHUBIN LIU ◽

YU XIAO ◽

...

Keyword(s):

Monte Carlo Simulation ◽

Monte Carlo ◽

Low Power ◽

High Speed ◽

Cmos Process ◽

Amplifier Circuit ◽

Offset Cancellation ◽

Offset Voltage ◽

Low Offset

A novel low offset, high speed, low power comparator architecture is proposed in this paper. In order to achieve low offset, both offset cancellation and dynamic amplifier techniques are adopted. Active resistors are chosen to implement the static amplifier circuit to obtain reduction in equivalent input referred offset voltage as well as to increase the circuit speed. The comparator is designed in TSMC 0.18 μm CMOS process. Monte Carlo simulation shows that the comparator has the offset voltage as low as 0.3 mV at 1 sigma at 250 MHz while dissipates 342 μW from a 1.8 V supply.

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Dynamic Offset Compensated Operational Amplifiers

10.36227/techrxiv.16810225 ◽

2021 ◽

Author(s):

Ara Abdulsatar Assim Assim ◽

Evgenii Balashov

Keyword(s):

Dynamic Range ◽

Flicker Noise ◽

Input Voltage ◽

High Gain ◽

Operational Amplifiers ◽

Analog To Digital ◽

Offset Cancellation ◽

Offset Voltage ◽

Low Offset ◽

The Given

The given work is devoted to designing and implementing different dynamic offset cancellation techniques for 50 nm technology CMOS operational amplifiers. The goal is to minimize or get rid of the effects of the offset voltage. Offset voltage exists in all differential amplifiers due to the fact that no pair of transistors can be fabricated with the same size, there is always a slight difference in their dimensions (length or width), this gives rise to an undesirable effect called offset, the value of offset voltage for cheap commercial amplifiers are in the range of 1 to 10 mV, de-spite the fact that this isn’t a significant value, due to the high gain of such amplifiers, this voltage is amplified by tens or hundreds of times, this results in clipping of the output signal and this further limits the amplifier’s maximum allowable input voltage within the given dynamic range, hence its of great importance to take this small voltage into consideration, low-offset amplifiers find applications in mixers, analog to digital converters, instrumentation devices, etc. In this thesis, by using two different techniques for removing offset voltage (chopping and auto-zeroing), five low offset operational amplifiers were designed. The implemented methods reduced the flicker noise by more than 457 times (from 9.4 nV/√Hz to 20 pV/√Hz) at 1 Hz. All the simulations were done using Cadence Virtuoso.

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A Low-Power Low-Distortion 20-GS/s Flash Analog-to-Digital Converter for Coherent Optical Receiver in 0.13-μm SiGe BiCMOS

Journal of Circuits System and Computers ◽

10.1142/s0218126619501676 ◽

2019 ◽

Vol 28 (10) ◽

pp. 1950167 ◽

Cited By ~ 1

Author(s):

Jiquan Li ◽

Yingmei Chen ◽

Pan Tang ◽

Zhen Zhang ◽

Hui Wang ◽

...

Keyword(s):

Power Consumption ◽

Low Power ◽

Optical Receiver ◽

Analog To Digital Converter ◽

Digital Converter ◽

Flash Adc ◽

Analog To Digital ◽

Offset Voltage ◽

Bicmos Technology ◽

Sige Bicmos

High-speed, low-power analog-to-digital converter (ADC) is a critical element for 5-GBd, 20-Gb/s digital signal processing (DSP)-based coherent optical communication receiver. To satisfy high data transmission rate requirement of optical receiver, a single-core and open-loop flash ADC with a new proposed multiplexer-based encoder is presented in this paper. Compared with conventional encoder topology, the new proposed topology achieves the fastest encoding speed and lowest power consumption. The optimized distortion is achieved by utilizing a leakage current compensation technique and a local negative feedback method in switched-buffer track-and-hold amplifier (THA). Strict synchronization is obtained for clock signals by careful designing of layout in tree-based clock networks. Furthermore, a master–slave comparator incorporated with a preamplifier reduces signal-dependent kickback noise as well as offset voltage. By using master–slave comparators and proposed encoders, the sampling rate is up to 21.12[Formula: see text]GS/s. The 4-bit, 20-GS/s flash ADC is realized in 0.13-[Formula: see text]m SiGe BiCMOS technology and it only occupies 1.05[Formula: see text]mm[Formula: see text][Formula: see text][Formula: see text]1.46[Formula: see text]mm chip area. With a power consumption of 1.831[Formula: see text]W from 4-V supply, the ADC achieves an effective number of bits (ENOB) of 2.5 at 15[Formula: see text]GS/s.

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A Switched-MOSFET Programmable Low-Voltage Filter

Journal of Integrated Circuits and Systems ◽

10.29292/jics.v1i1.252 ◽

2004 ◽

Vol 1 (1) ◽

pp. 32-37

Author(s):

Luís Cléber C. Marques ◽

Wouter A. Serdijn

Keyword(s):

Low Power ◽

Dynamic Range ◽

Low Voltage ◽

Supply Voltage ◽

Cmos Process ◽

Total Current ◽

Sampled Data ◽

Current Consumption ◽

Digitally Programmable ◽

Low Supply Voltage

This paper describes a digitally programmable low-voltage low-power analogue filter that can be used in hearing-aid circuits. The filter employs the recently introduced switched-MOSFET technique, a sampled-data technique suitable for low supply voltage operation since it avoids the conduction gap of the switches and does not need any dedicated process. The filter was implemented using the DIMES 1.6μm CMOS process and achieves 64 dB dynamic range. The total current consumption, drawn from a 2.2V supply, equals 93μA.

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Dynamic Offset Compensated Operational Amplifiers

10.36227/techrxiv.16810225.v1 ◽

2021 ◽

Author(s):

Ara Abdulsatar Assim Assim ◽

Evgenii Balashov

Keyword(s):

Dynamic Range ◽

Flicker Noise ◽

Input Voltage ◽

High Gain ◽

Operational Amplifiers ◽

Analog To Digital ◽

Offset Cancellation ◽

Offset Voltage ◽

Low Offset ◽

The Given

The given work is devoted to designing and implementing different dynamic offset cancellation techniques for 50 nm technology CMOS operational amplifiers. The goal is to minimize or get rid of the effects of the offset voltage. Offset voltage exists in all differential amplifiers due to the fact that no pair of transistors can be fabricated with the same size, there is always a slight difference in their dimensions (length or width), this gives rise to an undesirable effect called offset, the value of offset voltage for cheap commercial amplifiers are in the range of 1 to 10 mV, de-spite the fact that this isn’t a significant value, due to the high gain of such amplifiers, this voltage is amplified by tens or hundreds of times, this results in clipping of the output signal and this further limits the amplifier’s maximum allowable input voltage within the given dynamic range, hence its of great importance to take this small voltage into consideration, low-offset amplifiers find applications in mixers, analog to digital converters, instrumentation devices, etc. In this thesis, by using two different techniques for removing offset voltage (chopping and auto-zeroing), five low offset operational amplifiers were designed. The implemented methods reduced the flicker noise by more than 457 times (from 9.4 nV/√Hz to 20 pV/√Hz) at 1 Hz. All the simulations were done using Cadence Virtuoso.

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A High-Speed and Low-Offset Dynamic Latch Comparator

The Scientific World JOURNAL ◽

10.1155/2014/258068 ◽

2014 ◽

Vol 2014 ◽

pp. 1-8 ◽

Cited By ~ 9

Author(s):

Labonnah Farzana Rahman ◽

Mamun Bin Ibne Reaz ◽

Chia Chieu Yin ◽

Mohammad Marufuzzaman ◽

Mohammad Anisur Rahman

Keyword(s):

Monte Carlo Simulation ◽

Monte Carlo ◽

Power Dissipation ◽

High Speed ◽

Cmos Process ◽

Clock Frequency ◽

Analog To Digital ◽

Offset Voltage ◽

Simulation Results ◽

Low Offset

Circuit intricacy, speed, low-offset voltage, and resolution are essential factors for high-speed applications like analog-to-digital converters (ADCs). The comparator circuit with preamplifier increases the power dissipation, as it requires higher amount of currents than the latch circuitry. In this research, a novel topology of dynamic latch comparator is illustrated, which is able to provide high speed, low offset, and high resolution. Moreover, the circuit is able to reduce the power dissipation as the topology is based on latch circuitry. The cross-coupled circuit mechanism with the regenerative latch is employed for enhancing the dynamic latch comparator performance. In addition, input-tracking phase is used to reduce the offset voltage. The Monte-Carlo simulation results for the designed comparator in 0.18 μm CMOS process show that the equivalent input-referred offset voltage is 720 μV with 3.44 mV standard deviation. The simulated result shows that the designed comparator has 8-bit resolution and dissipates 158.5 μW of power under 1.8 V supply while operating with a clock frequency of 50 MHz. In addition, the proposed dynamic latch comparator has a layout size of148.80 μm×59.70 μm.

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A Low-Power 12-Bit 20 MS/s Asynchronously Controlled SAR ADC for WAVE ITS Sensor Based Applications

Sensors ◽

10.3390/s21072260 ◽

2021 ◽

Vol 21 (7) ◽

pp. 2260

Author(s):

Khuram Shehzad ◽

Deeksha Verma ◽

Danial Khan ◽

Qurat Ul Ain ◽

Muhammad Basim ◽

...

Keyword(s):

Power Consumption ◽

Low Power ◽

High Speed ◽

Intelligent Transportation System ◽

Cmos Process ◽

Process Technology ◽

Back Issue ◽

Digital To Analog Converter ◽

Analog To Digital ◽

Switching Method

A low power 12-bit, 20 MS/s asynchronously controlled successive approximation register (SAR) analog-to-digital converter (ADC) to be used in wireless access for vehicular environment (WAVE) intelligent transportation system (ITS) sensor based application is presented in this paper. To optimize the architecture with respect to power consumption and performance, several techniques are proposed. A switching method which employs the common mode charge recovery (CMCR) switching process is presented for capacitive digital-to-analog converter (CDAC) part to lower the switching energy. The switching technique proposed in our work consumes 56.3% less energy in comparison with conventional CMCR switching method. For high speed operation with low power consumption and to overcome the kick back issue in the comparator part, a mutated dynamic-latch comparator with cascode is implemented. In addition, to optimize the flexibility relating to the performance of logic part, an asynchronous topology is employed. The structure is fabricated in 65 nm CMOS process technology with an active area of 0.14 mm2. With a sampling frequency of 20 MS/s, the proposed architecture attains signal-to-noise distortion ratio (SNDR) of 65.44 dB at Nyquist frequency while consuming only 472.2 µW with 1 V power supply.

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