Design and performance analysis of low power LNA with variable gain current reuse technique

2021 ◽  
Author(s):  
Dheeraj Kalra ◽  
Vishal Goyal ◽  
Mayank Srivastava
Keyword(s):  
Performance Analysis ◽  
Low Power ◽  
Variable Gain ◽  
Current Reuse ◽  
And Performance

Aerodynamic and Performance Analysis of Representatives of One Century of Low Speed Aircraft

2014 ◽  
Vol 1016 ◽  
pp. 400-404
Author(s):  
Luciano Magno Fragola Barbosa ◽  
Paulo H. Iscold A. de Oliveira
Keyword(s):  
Performance Analysis ◽  
Comparative Study ◽  
Low Power ◽  
Reference Data ◽  
Performance Characteristics ◽  
Wing Loading ◽  
Low Speed ◽  
Data Basis ◽  
Low Weight ◽  
And Performance

This work presents a comparative study of aerodynamic and performance characteristics of relevant examples of low speed aircraft that have been built and flown between 1890 and 1990. As speed is related to aircraft mass and wing loading and power, the aircraft analyzed present low weight, low wing loading and low power. To generate this study a set of tools have been developed, which are specifically aimed to slow and light aircraft. One additional goal of the study is to obtain a consistent reference data basis - by using the developed tools to analyze existing aircraft - prior to use these tools in new designs with the features of low speed, low wing loading and low power.

scholarly journals Design and Performance Analysis of Low Power High Speed 4x4 CNTFET Binary Content Addressable Memory Array

2019 ◽  
Vol 9 (1) ◽  
pp. 5962-5965
Keyword(s):  
Performance Analysis ◽  
Low Power ◽  
High Speed ◽  
Peak Power ◽  
Average Power ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Content Addressable Memory ◽  
Power Peak ◽  
And Performance

In this paper, Carbon Nanotube Field Effect Transistor (CNTFET) based Binary Content Addressable Memory (BCAM) array is presented. The CAM array comprises of address decoders, encoders, data drivers and BCAM cells. Performance analysis is carried for 4X4 BCAM array. Each BCAM cell is designed based on adiabatic logic with optimum CNTFET parameter for low power and high speed applications. The performance of proposed BCAM array is analyzed for average power, peak power and search delay. The proposed CNTFET based BCAM array show improvement in the performance compared to that of complementary metal oxide semiconductor (CMOS) based BCAM array. The average power and peak power of the proposed 4x4 CNTFET BCAM array are in the range of micro watt (µW) while it is in the range of milli watt (mW) for CMOS based BCAM array. The search delay of the proposed 4X4 CNTFET BCAM array is improved by 32.3% compared to that of CMOS based BCAM array. All simulations are conducted for both CNTFET and CMOS based BCAM cells, BCAM array in HSPICE at 32 nm technology.

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