A Layout-Aware Pattern Grading Procedure for Critical Paths Considering Power Supply Noise and Crosstalk

Pattern grading for testing critical paths considering power supply noise and crosstalk using a layout-aware quality metric

Proceedings of the 20th symposium on Great lakes symposium on VLSI - GLSVLSI '10 ◽

10.1145/1785481.1785512 ◽

2010 ◽

Cited By ~ 2

Author(s):

Junxia Ma ◽

Jeremy Lee ◽

Mohammad Tehranipoor ◽

Nisar Ahmed ◽

Patrick Girard

Keyword(s):

Power Supply ◽

Power Supply Noise ◽

Quality Metric ◽

Pattern Grading ◽

Supply Noise ◽

Layout-aware pseudo-functional testing for critical paths considering power supply noise effects

2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) ◽

10.1109/date.2010.5457037 ◽

2010 ◽

Cited By ~ 3

Author(s):

Xiao Liu ◽

Yubin Zhang ◽

Feng Yuan ◽

Qiang Xu

Keyword(s):

Power Supply ◽

Functional Testing ◽

Power Supply Noise ◽

Noise Effects ◽

Supply Noise ◽

Maximizing Power Supply Noise on Critical Paths

Test and Diagnosis for Small-Delay Defects ◽

10.1007/978-1-4419-8297-1_8 ◽

2011 ◽

pp. 139-152

Author(s):

Mohammad Tehranipoor ◽

Ke Peng ◽

Krishnendu Chakrabarty

Keyword(s):

Power Supply ◽

Power Supply Noise ◽

Supply Noise ◽

AC Power Supply Noise Simulation of CMOS Microprocessor with LSI Chip-Package-Board Integrated Model

IEICE Transactions on Electronics ◽

10.1587/transele.e97.c.264 ◽

2014 ◽

Vol E97.C (4) ◽

pp. 264-271 ◽

Cited By ~ 1

Author(s):

Kumpei YOSHIKAWA ◽

Kouji ICHIKAWA ◽

Makoto NAGATA

Keyword(s):

Power Supply ◽

Integrated Model ◽

Power Supply Noise ◽

Supply Noise ◽

Noise Simulation ◽

Ac Power

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

Power-Supply-Noise-Aware Timing Analysis and Test Pattern Regeneration

10.1587/transfun.e99.a.2320 ◽

2016 ◽

Vol E99.A (12) ◽

pp. 2320-2327

Author(s):

Cheng-Yu HAN ◽

Yu-Ching LI ◽

Hao-Tien KAN ◽

James Chien-Mo LI

Keyword(s):

Power Supply ◽

Test Pattern ◽

Timing Analysis ◽

Power Supply Noise ◽

Power Supply Noise-Aware Scan Test Pattern Reshaping for At-Speed Delay Fault Testing of Monolithic 3D ICs *

2020 IEEE 29th Asian Test Symposium (ATS) ◽

10.1109/ats49688.2020.9301568 ◽

2020 ◽

Author(s):

Shao-Chun Hung ◽

Yi-Chen Lu ◽

Sung Kyu Lim ◽

Krishnendu Chakrabarty

Keyword(s):

Power Supply ◽

Test Pattern ◽

Power Supply Noise ◽

Fault Testing ◽

Delay Fault ◽

Delay Fault Testing ◽

3D Ics ◽

Scan Test ◽

A GALS Design with Opposite-Phase Local Clock Assignment for Power Supply Noise Reduction

2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) ◽

10.1109/apccas.2018.8605670 ◽

2018 ◽

Author(s):

Nguyen Van Toan ◽

Dam Minh Tung ◽

Jeong-Gun Lee

Keyword(s):

Noise Reduction ◽

Power Supply ◽

Power Supply Noise ◽

Local Clock ◽

Opposite Phase ◽

Single-chip multi-processor integrating quadruple 8-way vliw processors with interface timing analysis considering power supply noise

Asia and South Pacific Conference on Design Automation, 2006. ◽

10.1109/aspdac.2006.1594741 ◽

2006 ◽

Author(s):

S. Imai ◽

A. Inoue ◽

M. Matsumura ◽

K. Kawasaki ◽

A. Suga

Keyword(s):

Power Supply ◽

Timing Analysis ◽

Power Supply Noise ◽

Single Chip ◽

Vliw Processors ◽

Power supply noise in accurate delay model for the sub-threshold domain

Integration ◽

10.1016/j.vlsi.2015.02.001 ◽

2015 ◽

Vol 50 ◽

pp. 127-136

Author(s):

Pasquale Corsonello ◽

Fabio Frustaci ◽

Stefania Perri

Keyword(s):

Power Supply ◽

Delay Model ◽

Power Supply Noise ◽

Supply Noise ◽

Accurate Delay Model

Proceedings of the ASP-DAC Asia and South Pacific Design Automation Conference, 2003. ◽

Floorplanning with power supply noise avoidance

10.1109/aspdac.2003.1195053 ◽

2003 ◽

Cited By ~ 10

Author(s):

Hung-Ming Chen ◽

Li-Da Huang ◽

I-Min Liu ◽

Minghorng Lai ◽

D.F. Wong

Keyword(s):

Power Supply ◽

Power Supply Noise ◽