scholarly journals An Efficient Hardware-Based Fault-Tolerant Method for SMS4

2018 ◽  
Vol 208 ◽  
pp. 02005
Author(s):  
Hanguang Luo ◽  
Guangjun Wen ◽  
Jian Su
Keyword(s):  
Error Detection ◽  
Wireless Lan ◽  
Fault Tolerant ◽  
Low Cost ◽  
Primary Objective ◽  
Data Confidentiality ◽  
Detection Scheme ◽  
Detection Delay ◽  
Encryption Decryption ◽  
Online Error Detection

The SMS4 cryptosystem has been used in the Wireless LAN Authentication and Privacy Infrastructure (WAPI) standard for providing data confidentiality in China. So far, reliability has not been considered a primary objective in original version. However, a single fault in the encryption/decryption process can completely change the result of the cryptosystem no matter the natural or malicious injected faults. In this paper, we proposed low-cost structure-independent fault detection scheme for SMS4 cryptosystem which is capable of performing online error detection and can detect a single bit fault or odd multiple bit faults in coverage of 100 percent. Finally, the proposed techniques have been validated on Virtex-7 families FPGA platform to analyze its power consumption, overhead and time delay. It only needs 85 occupied Slices and 8.72mW to run a fault-tolerant scheme of SMS4 cryptosystem with 0.735ns of detection delay. Our new scheme increases in minimum redundancy to enhance cryptosystem’s reliability and achieve a better performance compared with the previous scheme.

A Flexible Fault Injection Platform for the Analysis of the Symptoms of Soft Errors in FPGA Soft Processors

2017 ◽  
Vol 26 (08) ◽  
pp. 1740009
Author(s):  
Aitzan Sari ◽  
Mihalis Psarakis
Keyword(s):  
Error Detection ◽  
Fault Tolerant ◽  
Fault Injection ◽  
Low Cost ◽  
Soft Errors ◽  
Soft Error ◽  
Detection Scheme ◽  
Detection Techniques ◽  
Error Sensitivity ◽  
Depth Analysis

Due to the high vulnerability of SRAM-based FPGAs in single-event upsets (SEUs), effective fault tolerant soft processor architectures must be considered when we use FPGAs to build embedded systems for critical applications. In the past, the detection of symptoms of soft errors in the behavior of microprocessors has been used for the implementation of low-budget error detection techniques, instead of costly hardware redundancy techniques. To enable the development of such low-cost error detection techniques for FPGA soft processors, we propose an in-depth analysis of the symptoms of SEUs in the FPGA configuration memory. To this end, we present a flexible fault injection platform based on an open-source CAD framework (RapidSmith) for the soft error sensitivity analysis of soft processors in Xilinx SRAM-based FPGAs. Our platform supports the estimation of soft error sensitivity per configuration bit/frame, processor component and benchmark. The fault injection is performed on-chip by a dedicated microcontroller which also monitors processor behavior to identify specific symptoms as consequences of soft errors. The performed analysis showed that these symptoms can be used to build an efficient, low-cost error detection scheme. The proposed platform is demonstrated through an extensive fault injection campaign in the Leon3 soft processor.

A new architecture for online error detection and isolation in network on chip

2020 ◽  
Vol 26 (4) ◽  
pp. 307-323
Author(s):  
Chakib Nehnouh
Keyword(s):  
Error Detection ◽  
Fault Tolerant ◽  
High Reliability ◽  
Low Cost ◽  
Network On Chip ◽  
Fault Detection And Isolation ◽  
Main Concern ◽  
Transient Faults ◽  
Protection Factor ◽  
On Chip

The Network-on-Chip (NoC) has become a promising communication infrastructure for Multiprocessors-System-on-Chip (MPSoC). Reliability is a main concern in NoC and performance is degraded when NoC is susceptible to faults. A fault can be determined as a cause of deviation from the desired operation of the system (error). To deal with these reliability challenges, this work propose OFDIM (Online Fault Detection and Isolation Mechanism),a novel combined methodology to tolerate multiple permanent and transient faults. The new router architecture uses two modules to assure highly reliable and low-cost fault-tolerant strategy. In contrast to existing works, our architecture presents less area, more fault tolerance, and high reliability. The reliability comparison using Silicon Protection Factor (SPF), shows 22-time improvement and that additional circuitry incurs an area overhead of 27%, which is better than state-of-the-art reliable router architectures. Also, the results show that the throughput decreases only by 5.19% and minor increase in average latency 2.40% while providing high reliability.

scholarly journals Fault-tolerant detection of a quantum error

Science ◽  
2018 ◽  
Vol 361 (6399) ◽  
pp. 266-270 ◽  
Author(s):  
S. Rosenblum ◽  
P. Reinhold ◽  
M. Mirrahimi ◽  
Liang Jiang ◽  
L. Frunzio ◽  
...  
Keyword(s):  
Error Detection ◽  
Fault Tolerant ◽  
Critical Component ◽  
Detection Scheme ◽  
Dephasing Time ◽  
Order Of Magnitude ◽  
Quantum Error ◽  
Specific Error ◽  
Logical Qubit

A critical component of any quantum error–correcting scheme is detection of errors by using an ancilla system. However, errors occurring in the ancilla can propagate onto the logical qubit, irreversibly corrupting the encoded information. We demonstrate a fault-tolerant error-detection scheme that suppresses spreading of ancilla errors by a factor of 5, while maintaining the assignment fidelity. The same method is used to prevent propagation of ancilla excitations, increasing the logical qubit dephasing time by an order of magnitude. Our approach is hardware-efficient, as it uses a single multilevel transmon ancilla and a cavity-encoded logical qubit, whose interaction is engineered in situ by using an off-resonant sideband drive. The results demonstrate that hardware-efficient approaches that exploit system-specific error models can yield advances toward fault-tolerant quantum computation.

On Using Approximate Computing to Build an Error Detection Scheme for Arithmetic Circuits

2020 ◽  
Vol 36 (1) ◽  
pp. 33-46
Author(s):  
B. Deveautour ◽  
A. Virazel ◽  
P. Girard ◽  
V. Gherman
Keyword(s):  
Error Detection ◽  
Arithmetic Circuits ◽  
Approximate Computing ◽  
Detection Scheme

Setting an error detection infrastructure with low cost acoustic wave detectors

2012 ◽  
Vol 40 (3) ◽  
pp. 333-343 ◽  
Author(s):  
Gaurang Upasani ◽  
Xavier Vera ◽  
Antonio González
Keyword(s):  
Acoustic Wave ◽  
Error Detection ◽  
Low Cost

scholarly journals Exponential suppression of bit or phase errors with cyclic error correction

Nature ◽  
2021 ◽  
Vol 595 (7867) ◽  
pp. 383-387
Author(s):  
◽  
Zijun Chen ◽  
Kevin J. Satzinger ◽  
Juan Atalaya ◽  
Alexander N. Korotkov ◽  
...  
Keyword(s):  
Error Correction ◽  
Error Detection ◽  
Fault Tolerant ◽  
Error Rates ◽  
Quantum Error Correction ◽  
Superconducting Qubits ◽  
Two Dimensional ◽  
Logical Error ◽  
Quantum Error ◽  
Logical Qubit

AbstractRealizing the potential of quantum computing requires sufficiently low logical error rates1. Many applications call for error rates as low as 10−15 (refs. 2–9), but state-of-the-art quantum platforms typically have physical error rates near 10−3 (refs. 10–14). Quantum error correction15–17 promises to bridge this divide by distributing quantum logical information across many physical qubits in such a way that errors can be detected and corrected. Errors on the encoded logical qubit state can be exponentially suppressed as the number of physical qubits grows, provided that the physical error rates are below a certain threshold and stable over the course of a computation. Here we implement one-dimensional repetition codes embedded in a two-dimensional grid of superconducting qubits that demonstrate exponential suppression of bit-flip or phase-flip errors, reducing logical error per round more than 100-fold when increasing the number of qubits from 5 to 21. Crucially, this error suppression is stable over 50 rounds of error correction. We also introduce a method for analysing error correlations with high precision, allowing us to characterize error locality while performing quantum error correction. Finally, we perform error detection with a small logical qubit using the 2D surface code on the same device18,19 and show that the results from both one- and two-dimensional codes agree with numerical simulations that use a simple depolarizing error model. These experimental demonstrations provide a foundation for building a scalable fault-tolerant quantum computer with superconducting qubits.

Development of All-Plastic Microvalve Array for Multiplexed Immunoassay

2014 ◽  
Author(s):  
Shancy Augustine ◽  
Pan Gu ◽  
Xiangjun Zheng ◽  
Toshikazu Nishida ◽  
Z. Hugh Fan
Keyword(s):  
Large Scale ◽  
Low Cost ◽  
Simultaneous Detection ◽  
Cost Effective ◽  
Negative Control ◽  
Sensitive Material ◽  
Detection Scheme ◽  
Power Battery ◽  
Multiple Analytes ◽  
Multiplexed Immunoassay

There is a need for low-cost immunoassays that measure the presence and concentration of multiple harmful agents in one device. Currently, comparable immunoassays employ a one-analyte-per-test format that is time consuming and not cost effective for the requirement of detecting multiple analytes in a single sample. For instance, if a spectrum of harmful agents, including E. coli O157, cholera toxin, and Salmonella typhimurium, should be simultaneously monitored in foods and drinking water, then a one-analyte-per-test would be inefficient. This work demonstrates a platform capable of simultaneous detection of multiple analytes in a single, low-cost, microvalve array-enabled multiplexed immunoassay. This multiplexed immunoassay platform is demonstrated in a prototype COC (cyclic olefin copolymer) device with a 2×3 array in which 6 analytes can be detected simultaneously. In order to contain and regulate the flow of reagents in the multichannel device, an array of microfluidic valves actuated by a thermally expandable material and microfabricated resistors have been developed to direct the flow to the necessary assay sites. The microvalve-based immunoassay is shown to be reliable, easy to operate, and compatible with large-scale integration. The all-plastic microvalves use paraffin wax as the thermally sensitive material which drastically reduces power consumption by latching upon closing so that pulsed power is required only to close and latch the microvalve until it is necessary to re-open the valve. The multiplexed detection scheme has been demonstrated by using three proteins, C reactive protein (CRP) and transferrin, both of which are biomarkers associated with traumatic brain injury (TBI) as well as bovine serum albumin (BSA) as the negative control. Since there are no external bulky pneumatic accessories required to operate/latch the microvalves in the device, this compact, thermally actuated and latching microvalve-enabled multiplexed immunoassay has the potential to realize a portable, low power, battery operated microfluidic device for biological assays.

scholarly journals Exploiting Existing Comparators for Fine-Grained Low-Cost Error Detection

2014 ◽  
Vol 11 (3) ◽  
pp. 1-24
Author(s):  
Gulay Yalcin ◽  
Oguz Ergin ◽  
Emrah Islek ◽  
Osman Sabri Unsal ◽  
Adrian Cristal
Keyword(s):  
Error Detection ◽  
Low Cost ◽  
Fine Grained
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