Electrical properties of a metal-germanium-topological insulator (metal/n-Ge/p-Bi2Te3) heterostructure devices

2021 ◽  
Vol 32 (6) ◽  
pp. 8106-8121
Author(s):  
Faizan Ahmad ◽  
Kavindra Kandpal ◽  
Pramod Kumar
2013 ◽  
Vol 709 ◽  
pp. 172-175
Author(s):  
Li Lv ◽  
Min Zhang ◽  
Li Qin Yang ◽  
Xin Sheng Yang ◽  
Yong Zhao

Single crystals of Bi2Se3 topological insulators have been prepared though melt-grown reaction. The sintering parameters of holding time and cooling rate obviously affect the phase structure and electrical properties. The samples with layered structure can be perpendicular cleaved with (0 0 L) axis. All the samples show n-type conductivity caused by the existence of Se vacancies. For low cooling rate, more Se atoms anti-occupy Bi lattice sites, which decreases c-axis lattice parameter and increases carrier concentration n; high cooling rate increases c and decreases n because of less Se atoms occupying Bi lattice sites. Increasing holding time firstly decreases the ratio of Se atoms occupying Bi lattice sites and then increases it, which gives rise to c firstly increase then decrease and n firstly decrease then increase.


2013 ◽  
Vol 103 (20) ◽  
pp. 202409 ◽  
Author(s):  
A. Kandala ◽  
A. Richardella ◽  
D. W. Rench ◽  
D. M. Zhang ◽  
T. C. Flanagan ◽  
...  

2019 ◽  
Author(s):  
Joanna Sitnicka ◽  
Marcin Konczykowski ◽  
Anna Reszka ◽  
Pawel Skupinski ◽  
Krzysztof Grasza ◽  
...  

Author(s):  
F. M. Ross ◽  
R. Hull ◽  
D. Bahnck ◽  
J. C. Bean ◽  
L. J. Peticolas ◽  
...  

We describe an investigation of the electrical properties of interfacial dislocations in strained layer heterostructures. We have been measuring both the structural and electrical characteristics of strained layer p-n junction diodes simultaneously in a transmission electron microscope, enabling us to correlate changes in the electrical characteristics of a device with the formation of dislocations.The presence of dislocations within an electronic device is known to degrade the device performance. This degradation is of increasing significance in the design and processing of novel strained layer devices which may require layer thicknesses above the critical thickness (hc), where it is energetically favourable for the layers to relax by the formation of misfit dislocations at the strained interfaces. In order to quantify how device performance is affected when relaxation occurs we have therefore been investigating the electrical properties of dislocations at the p-n junction in Si/GeSi diodes.


Author(s):  
A.M. Letsoalo ◽  
M.E. Lee ◽  
E.O. de Neijs

Semiconductor devices require metal contacts for efficient collection of electrical charge. The physics of these metal/semiconductor contacts assumes perfect, abrupt and continuous interfaces between the layers. However, in practice these layers are neither continuous nor abrupt due to poor nucleation conditions and the formation of interfacial layers. The effects of layer thickness, deposition rate and substrate stoichiometry have been previously reported. In this work we will compare the effects of a single deposition technique and multiple depositions on the morphology of indium layers grown on (100) CdTe substrates. The electrical characteristics and specific resistivities of the indium contacts were measured, and their relationships with indium layer morphologies were established.Semi-insulating (100) CdTe samples were cut from Bridgman grown single crystal ingots. The surface of the as-cut slices were mechanically polished using 5μm, 3μm, 1μm and 0,25μm diamond abrasive respectively. This was followed by two minutes immersion in a 5% bromine-methanol solution.


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