Design of reversible parity generator and checker for the implementation of nano-communication systems in quantum-dot cellular automata

2019 ◽  
Vol 38 (2) ◽  
pp. 231-243 ◽  
Author(s):  
Ali Norouzi ◽  
Saeed Rasouli Heikalabad
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Communication Systems ◽  
Quantum Dot Cellular Automata ◽  
Parity Generator

scholarly journals Gray‐code adder with parity generator – a novel quantum‐dot cellular automata implementation

2020 ◽  
Vol 14 (2) ◽  
pp. 243-250 ◽  
Author(s):  
Luiz G.L. Vieira ◽  
Luiz F.M. Vieira ◽  
Marcos A.M. Vieira ◽  
Omar P. Vilela Neto
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Gray Code ◽  
Quantum Dot Cellular Automata ◽  
Parity Generator

scholarly journals Design and Evaluation of Cell Interaction Based Vedic Multiplier Using Quantum-Dot Cellular Automata

Electronics ◽  
2020 ◽  
Vol 9 (6) ◽  
pp. 1036
Author(s):  
Nuriddin Safoev ◽  
Jun-Cheol Jeon
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Communication Networks ◽  
Communication Systems ◽  
High Speed ◽  
Digital Signal ◽  
Cell Interaction ◽  
Quantum Dot Cellular Automata ◽  
Vedic Multiplier ◽  
Ripple Carry Adder

A multiplier is one of the main units for digital signal processing and communication systems. In this paper, a high speed and low complexity multiplier is designed on the basis of quantum-dot cellular automata (QCA), which is considered promising nanotechnology. We focus on Vedic multiplier architectures according to Vedic mathematics from ancient Indian sculptures. In fact, an adder is an important block in the design of almost all types of multipliers and a ripple carry adder is used to design simple multiplier implementations. However, a high-speed multi-bit multiplier requires high-speed adder owing to carry propagation. Cell-interaction-based QCA adders have better improvements over conventional majority-gate-based adders. Therefore, a two-bit Vedic multiplier is proposed in QCA and it is used to implement a four-bit form of the multiplier. The proposed architecture has a lower cell count and area compared to other existing structures. Moreover, simulation results demonstrate that the proposed design is sustainable and can be used to realize complex circuit designs for QCA communication networks.

Design & Analysis of Novel Non-Reversible & Reversible Parity Generator & Detector in Quantum Cellular Automata using Feynman Gate

2021 ◽  
Vol 13 ◽  
Author(s):  
Neeraj Tripathi ◽  
Mohammad Mudakir Fazili ◽  
Rahil Jahangir
Keyword(s):  
Energy Dissipation ◽  
Cellular Automata ◽  
Quantum Dot ◽  
Low Power ◽  
Fault Tolerant ◽  
Design Parameters ◽  
Logic Function ◽  
Ultra Low Power ◽  
Quantum Dot Cellular Automata ◽  
Parity Generator

Aim: A novel design for non-reversible as well as reversible parity generator and detector in Quantum-dot Cellular Automata (QCA) technology is presented in this research article. Parity generator and detector circuits are reliable error-checking components of a nano-communication system. Objective: The main focus of this research is to design an ultra-low-power fault-tolerant reversible gate implementation of the parity logic function in QCA. An efficient QCA design layout with minimal area, less latency and the least energy dissipation is desired. Methods: The proposed designs are developed using Quantum-dot Cellular Automata (QCA) technology. The circuits are optimized using majority gate reduction and clock zone reduction techniques. Also, the cell-cell interaction technique is employed to further optimize the QCA circuit. To increase the fault tolerance and for ultra-low power operation, reversible QCA circuits are designed using cascaded Feynman gates. Results and Conclusion: The efficiency of the parity generator and detector is calculated to be more than 25% compared to existing QCA layouts. It is demonstrated in this paper that the proposed circuits perform exceptionally well on every design parameter. The design parameters under consideration are cell count, cell area, complexity, crossover count, latency and energy dissipation. Using reversible logic, a fault-tolerant and defect-sensitive circuit is developed for parity generation and detection.

Improved Quantum Dot Cellular Automata 4:1 Multiplexer Circuit Unit

2014 ◽  
Vol 2014 (1) ◽  
pp. 37-44 ◽  
Author(s):  
Arighna Sarkar ◽  
◽  
Debarka Mukhopadhyay ◽  
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Quantum Dot Cellular Automata
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