logic function
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Electronics ◽  
2021 ◽  
Vol 11 (1) ◽  
pp. 27
Author(s):  
Raouf Senhadji-Navarro ◽  
Ignacio Garcia-Vargas

Current Field Programmable Gate Arrays (FPGAs) provide fast routing links and special logic to perform carry operations; however, these resources can also be used to implement non-arithmetic circuits. In this paper, a new approach for mapping logic functions onto carry chains is presented. Unlike other approaches, the proposed technique can be applied to any logic function. The presented technique includes: (1) an architecture that is composed of blocks that implement AND and OR functions (called CANDs and CORs, respectively) by means of Look-Up-Tables (LUTs) and carry-chain resources; and (2) a mapping algorithm to reduce both the delay of the critical path and the number of used FPGA resources. The algorithm uses a heuristic to interconnect CORs and CANDs in order to reduce the delay. The problem of mapping the maxterms (or minterms) of a function to LUTs has been modelled as a Set Bin Packing (SBP) problem. Since SBP is NP-Hard, a greedy algorithm has been proposed, which is based on the First Fit Decreasing (FFD) heuristic. The results obtained have been compared with the conventional technique using both speed and area optimization. For this purpose, a large synthetic set of test cases has been generated. The proposed technique improves both the speed and area results for the vast majority of functions whose conventional implementation requires more than four logic levels. It is important to highlight that the improvement of one parameter (speed or area) is not achieved at the expense of the other.


Author(s):  
Akambay Beisembayev ◽  
Anargul Yerbossynova ◽  
Petro Pavlenko ◽  
Mukhit Baibatshayev

This paper reports a method, built in the form of a logic function, for describing the working spaces of manipulation robots analytically. A working space is defined as a work area or reachable area by a manipulation robot. An example of describing the working space of a manipulation robot with seven rotational degrees of mobility has been considered. Technological processes in robotic industries can be associated with the positioning of the grip, at the required points, in the predefined coordinates, or with the execution of the movement of a working body along the predefined trajectories, which can also be determined using the required points in the predefined coordinates. A necessary condition for a manipulation robot to execute a specified process is that all the required positioning points should be within a working space. To solve this task, a method is proposed that involves the analysis of the kinematic scheme of a manipulation robot in order to acquire a graphic image of the working space to identify boundary surfaces, as well as identify additional surfaces. The working space is limited by a set of boundary surfaces where additional surfaces are needed to highlight parts of the working space. Specifying each surface as a logic function, the working space is described piece by piece. Next, the resulting parts are combined with a logical expression, which is a disjunctive normal form of logic functions, which is an analytical description of the working space. The correspondence of the obtained analytical description to the original graphic image of working space is verified by simulating the disjunctive normal form of logic functions using MATLAB (USA).


2021 ◽  
Vol 12 (9) ◽  
pp. s741-s773
Author(s):  
Adriana Comanescu ◽  
Alexandra Rotaru ◽  
Florian Ion Tiberiu Petrescu

The paper presents in detail a method of calculating the forces acting on a 2T9R type robot. In order to determine the reactions (forces in the kinematic couples), one must first determine the inertial forces in the mechanism to which one or more useful loads of the robot can be added. The torsor of the inertia forces is calculated with the help of the masses of the machine elements and the accelerations from the centers of mass of the mechanism elements, so the positions, velocities, and accelerations acting on it will be determined, i.e. its complete kinematics. The calculation method applied by a MathCad program intelligently uses data entry through the IFLOG logic function so that the calculations can be automated. So the effective automation of the calculation program is done exclusively through the IFLOG functions originally used in the paper.


Author(s):  
Walter C. Daugherity ◽  
Laszlo B. Kish

We point out that the exponentially fast, grounding-based search scheme in noise-based logic works mostly on core superpositions. When the superposition contains elements that are outputs of logic gate operations, the search result can be erroneous, because grounding of a reference bit can change a logic function too. Adding superpositions with a search bit of inverted signal amplitude sign (sign inversion instead of grounding) can fix the problem in special cases, but a general solution is yet to be found. Note that because phonebooks are core superpositions, the original search algorithm remains valid for phonebook lookups, for both name and number search, including fractions of names or numbers.


2021 ◽  
Vol 2021 ◽  
pp. 1-11
Author(s):  
Ye Hao ◽  
Jiang Zhidi ◽  
Hu Jianping

In this paper, we propose a new type of tri-input tunneling field-effect transistor (Ti-TFET) that can compactly realize the “Majority-Not” logic function with a single transistor. It features an ingenious T-shaped channel and three independent-biasing gates deposited and patterned on its left, right, and upper sides, which greatly enhance the electrostatic control ability between any two gates of all the three gates on the device channel and thus increase its turn-on current. The total current density and energy band distribution in different biasing conditions are analyzed in detail by TCAD simulations. The turn-on current, leakage current, and ratio of turn-on/off current are optimized by choosing appropriate work function and body thickness. TCAD simulation results verify the expected characteristics of the proposed Ti-TFETs in different working states. Ti-TFETs can flexibly be used to implement a logic circuit with a compact style and thus reduce the number of transistors and stack height of the circuits. It provides a new technique to reduce the chip area and power consumption by saving the number of transistors.


2021 ◽  
Author(s):  
Barak Hoffer ◽  
Nicolás Wainstein ◽  
Christopher M. Neumann ◽  
Eric Pop ◽  
Eilam Yalon ◽  
...  

Abstract Stateful logic is a digital processing-in-memory technique that could address von Neumann memory bottleneck challenges while maintaining backward compatibility with von Neumann architectures. In stateful logic, memory cells are used to perform the logic operations without reading or moving any data outside the memory array. This has been previously demonstrated using several resistive memory types, but not with commercially available phase-change memory (PCM). Here we present the first implementation of stateful logic using PCM. We experimentally demonstrate four logic gate types (NOR, IMPLY, OR, NIMP) using commonly used PCM materials and crossbar-compatible structures. Our stateful logic gates form a functionally complete set, which enables sequential execution of any logic function within the memory and paves the way to PCM-based digital processing-in-memory systems.


Frequenz ◽  
2021 ◽  
Vol 0 (0) ◽  
Author(s):  
Mohamed Salah Bouaouina ◽  
Mohamed Redha Lebbal ◽  
Mohamed Bouchemat ◽  
Touraya Bouchemat

Abstract Nowadays, the development of optical telecommunication systems requires more efficient all-optical elements appreciation to their high data transmission speeds and reduced electromagnetic interferences. In this work, our objective is to attest by simulation a design of an optical switch using 2D photonic crystals from polystyrene, an organic polymeric material with high Kerr non-linearity. This excellent ultra-fast switching leads us to the exploited in the construction of two new structures of all-optical AND/NAND and OR/NOR logic gates. These structures based on non-linear ring resonator NRR of different radius in order to operate a telecom wavelength of 1550.3 µm using RSoft (Full-Wave) software. The average contrast intensity is between 15.52 and 23.42 dB and low delay time varied from 20 fs to 5.0 ps. Hence, resulting a very high output signal for ON-switching (82–130% of P in) and a weak signal for OFF-switching (0.2–7% of P in) through a minimum threshold power around of 1.2 mW/μm2.


2021 ◽  
pp. 365-373
Author(s):  
Sergey F. Tyurin ◽  
Ruslan V. Vikhorev

The FPGA (Field-Programmable Gate Array) has recently become the popular hardware and so-called LUTs (Look up Tables) are the basic of the FPGAs logic. For example, n-LUT is the MOS pass transistors multiplexer 2n-1 which input data receive SRAM cells logic function configuration (user’s projects Truth Table). Address inputs of the LUT are the variables. Therefore, we get one n-arguments logic function for the actual FPGA configuration. To get m functions (even with the same n-arguments) we should take m LUT. Authors propose a novel Decoder n-LUT (n-DC LUT), which makes possible to get m functions with the same n-arguments, like in Program Logic Array (PLA) CPLD (Complex Programmable Logic Device). DC LUT activates one of the 2n product terms outputs. Combined with OR product terms we can get m functions with the same n-arguments. To do this option we can use, for example, FPGAs typical connections units. The restriction of Meade-Conway for the FPGAs allows n=3 in one tree. Two 3-LUTs with one 1-LUTs form 4-LUT. Modern Adaptive Logic Modules (ALM) have n=8, but not all possible functions are implemented. The article deals with the design and investigation of some variants 3-DC LUT: with pull up output resistors, with orthogonal output circuits, with orthogonal transistors for each pass transistor. Simulation confirms the feasibility of the proposed method and shows that DC LUT with orthogonal output circuits is better variant of the systems realization in terms of current consumption and time delay at large n. A further development of the ALM concept may be the introduction of adaptive DC LUT, which, by tuning, can calculate single LUT function or 2n decoder functions. The proposed elements allow to increase the functionality of the FPGAs.


2021 ◽  
Author(s):  
Abdulqader Mahmoud ◽  
Frederic Vanderveken ◽  
Christoph Adelmann ◽  
Florin Ciubotaru ◽  
Said Hamdioui ◽  
...  

By its very nature, Spin Wave (SW) interference provides intrinsic support for Majority logic function evaluation. Due to this and the fact that the 3-input Majority (MAJ3) gate and the Inverter constitute a universal Boolean logic gate set, different MAJ3 gate implementations have been proposed. However, they cannot be directly utilized for the construction of larger SW logic circuits as they lack a key cascading mechanism, i.e., fan-out capability. In this paper, we introduce a novel ladder-shaped SW MAJ3 gate design able to provide a maximum fan-out of 2 (FO2). The proper gate functionality is validated by means of micromagnetic simulations, which also demonstrate that the amplitude mismatch between the two outputs is negligible proving that an FO2 is properly achieved. Additionally, we evaluate the gate area and compare it with SW state-of-the-art and 15nm CMOS counterparts working under the same conditions. Our results indicate that the proposed structure requires 12x less area than the 15 nm CMOS MAJ3 gate and that at the gate level the fan-out capability results in 16% area savings, when compared with the state-of-the-art SW majority gate counterparts.


2021 ◽  
Author(s):  
Abdulqader Mahmoud ◽  
Frederic Vanderveken ◽  
Christoph Adelmann ◽  
Florin Ciubotaru ◽  
Said Hamdioui ◽  
...  

By its very nature, Spin Wave (SW) interference provides intrinsic support for Majority logic function evaluation. Due to this and the fact that the 3-input Majority (MAJ3) gate and the Inverter constitute a universal Boolean logic gate set, different MAJ3 gate implementations have been proposed. However, they cannot be directly utilized for the construction of larger SW logic circuits as they lack a key cascading mechanism, i.e., fan-out capability. In this paper, we introduce a novel ladder-shaped SW MAJ3 gate design able to provide a maximum fan-out of 2 (FO2). The proper gate functionality is validated by means of micromagnetic simulations, which also demonstrate that the amplitude mismatch between the two outputs is negligible proving that an FO2 is properly achieved. Additionally, we evaluate the gate area and compare it with SW state-of-the-art and 15nm CMOS counterparts working under the same conditions. Our results indicate that the proposed structure requires 12x less area than the 15 nm CMOS MAJ3 gate and that at the gate level the fan-out capability results in 16% area savings, when compared with the state-of-the-art SW majority gate counterparts.


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