High-performance fieldbus application-specific integrated circuit design for industrial smart sensor networks

2017 ◽  
Vol 74 (9) ◽  
pp. 4451-4469 ◽  
Author(s):  
Ching-Han Chen ◽  
Ming-Yi Lin ◽  
Xing-Chen Guo
Keyword(s):  
Sensor Networks ◽  
Circuit Design ◽  
Integrated Circuit ◽  
High Performance ◽  
Smart Sensor ◽  
Integrated Circuit Design ◽  
Application Specific Integrated Circuit ◽  
Application Specific

Cell libraries and assembly tools for analog/digital CMOS and BiCMOS application-specific integrated circuit design

1989 ◽  
Vol 24 (5) ◽  
pp. 1419-1432 ◽  
Author(s):  
M.J.S. Smith ◽  
C. Portmann ◽  
C. Anagnostopoulos ◽  
P.S. Tschang ◽  
R. Rao ◽  
...  
Keyword(s):  
Circuit Design ◽  
Integrated Circuit ◽  
Digital Cmos ◽  
Integrated Circuit Design ◽  
Application Specific Integrated Circuit ◽  
Application Specific

scholarly journals A P4-Enabled RINA Interior Router for Software-Defined Data Centers

Computers ◽  
2020 ◽  
Vol 9 (3) ◽  
pp. 70
Author(s):  
Carolina Fernández ◽  
Sergio Giménez ◽  
Eduard Grasa ◽  
Steve Bunch
Keyword(s):  
Integrated Circuit ◽  
High Performance ◽  
Data Transfer ◽  
Great Promise ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Application Specific Integrated Circuit ◽  
Networking Technologies ◽  
Application Specific

The lack of high-performance RINA (Recursive InterNetwork Architecture) implementations to date makes it hard to experiment with RINA as an underlay networking fabric solution for different types of networks, and to assess RINA’s benefits in practice on scenarios with high traffic loads. High-performance router implementations typically require dedicated hardware support, such as FPGAs (Field Programmable Gate Arrays) or specialized ASICs (Application Specific Integrated Circuit). With the advance of hardware programmability in recent years, new possibilities unfold to prototype novel networking technologies. In particular, the use of the P4 programming language for programmable ASICs holds great promise for developing a RINA router. This paper details the design and part of the implementation of the first P4-based RINA interior router, which reuses the layer management components of the IRATI Linux-based RINA implementation and implements the data-transfer components using a P4 program. We also describe the configuration and testing of our initial deployment scenarios, using ancillary open-source tools such as the P4 reference test software switch (BMv2) or the P4Runtime API.

Application of Photoemission Microscopy and Focused Ion Beam Microsurgery to an Investigation of Latchup

1996 ◽  
Author(s):  
D.C. Mayer ◽  
R.J. Ferro ◽  
D.L. Leung ◽  
M.A. Dooley ◽  
J.R. Scarpulla
Keyword(s):  
Integrated Circuit ◽  
High Performance ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Commercial Application ◽  
Input Buffer ◽  
Before And After ◽  
Application Specific Integrated Circuit ◽  
Radiation Induced ◽  
Application Specific

Abstract Radiation-induced latchup sites in a high-performance commercial application-specific integrated circuit (ASIC) manufactured in a bipolar gate array have been identified using a photoemission (PE) microscope before and after isolating individual circuit elements with a focused ion beam (FIB) system. Latchup sites were determined to be associated with grounded unused resistors and transistors in an emitter-coupled logic (ECL) input buffer. Simulation of the oxide isolation scheme confirmed the presence of pnpn structures at the likely latchup sites. A corrective action to redesign the layouts to disconnect unused resistors and transistors resulted in successful elimination of latchup in the ECL buffers.

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