scholarly journals A High-Performance Application Specific Integrated Circuit for Electrical and Neurochemical Traumatic Brain Injury Monitoring

ChemPhysChem ◽  
2018 ◽  
Vol 19 (10) ◽  
pp. 1215-1225 ◽  
Author(s):  
Ilias Pagkalos ◽  
Michelle L. Rogers ◽  
Martyn G. Boutelle ◽  
Emmanuel M. Drakakis
Keyword(s):  
Traumatic Brain Injury ◽  
Brain Injury ◽  
Integrated Circuit ◽  
High Performance ◽  
Application Specific Integrated Circuit ◽  
High Performance Application ◽  
Application Specific

scholarly journals A P4-Enabled RINA Interior Router for Software-Defined Data Centers

Computers ◽  
2020 ◽  
Vol 9 (3) ◽  
pp. 70
Author(s):  
Carolina Fernández ◽  
Sergio Giménez ◽  
Eduard Grasa ◽  
Steve Bunch
Keyword(s):  
Integrated Circuit ◽  
High Performance ◽  
Data Transfer ◽  
Great Promise ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Application Specific Integrated Circuit ◽  
Networking Technologies ◽  
Application Specific

The lack of high-performance RINA (Recursive InterNetwork Architecture) implementations to date makes it hard to experiment with RINA as an underlay networking fabric solution for different types of networks, and to assess RINA’s benefits in practice on scenarios with high traffic loads. High-performance router implementations typically require dedicated hardware support, such as FPGAs (Field Programmable Gate Arrays) or specialized ASICs (Application Specific Integrated Circuit). With the advance of hardware programmability in recent years, new possibilities unfold to prototype novel networking technologies. In particular, the use of the P4 programming language for programmable ASICs holds great promise for developing a RINA router. This paper details the design and part of the implementation of the first P4-based RINA interior router, which reuses the layer management components of the IRATI Linux-based RINA implementation and implements the data-transfer components using a P4 program. We also describe the configuration and testing of our initial deployment scenarios, using ancillary open-source tools such as the P4 reference test software switch (BMv2) or the P4Runtime API.

Application of Photoemission Microscopy and Focused Ion Beam Microsurgery to an Investigation of Latchup

1996 ◽  
Author(s):  
D.C. Mayer ◽  
R.J. Ferro ◽  
D.L. Leung ◽  
M.A. Dooley ◽  
J.R. Scarpulla
Keyword(s):  
Integrated Circuit ◽  
High Performance ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Commercial Application ◽  
Input Buffer ◽  
Before And After ◽  
Application Specific Integrated Circuit ◽  
Radiation Induced ◽  
Application Specific

Abstract Radiation-induced latchup sites in a high-performance commercial application-specific integrated circuit (ASIC) manufactured in a bipolar gate array have been identified using a photoemission (PE) microscope before and after isolating individual circuit elements with a focused ion beam (FIB) system. Latchup sites were determined to be associated with grounded unused resistors and transistors in an emitter-coupled logic (ECL) input buffer. Simulation of the oxide isolation scheme confirmed the presence of pnpn structures at the likely latchup sites. A corrective action to redesign the layouts to disconnect unused resistors and transistors resulted in successful elimination of latchup in the ECL buffers.

scholarly journals Simultaneous Voltage and Current Measurement Instrumentation Amplifier for ECG and PPG Monitoring

Electronics ◽  
2021 ◽  
Vol 10 (6) ◽  
pp. 679
Author(s):  
Jongpal Kim
Keyword(s):  
Integrated Circuit ◽  
Cardiovascular Health ◽  
Current Noise ◽  
Instrumentation Amplifier ◽  
Current Sensing ◽  
Application Specific Integrated Circuit ◽  
Time Division ◽  
Electrocardiogram Ecg ◽  
First Time ◽  
Application Specific

An instrumentation amplifier (IA) capable of sensing both voltage and current at the same time has been introduced and applied to electrocardiogram (ECG) and photoplethysmogram (PPG) measurements for cardiovascular health monitoring applications. The proposed IA can switch between the voltage and current sensing configurations in a time–division manner faster than the ECG and PPG bandwidths. The application-specific integrated circuit (ASIC) of the proposed circuit design was implemented using 180 nm CMOS fabrication technology. Input-referred voltage noise and current noise were measured as 3.9 µVrms and 172 pArms, respectively, and power consumption was measured as 34.9 µA. In the current sensing configuration, a current noise reduction technique is applied, which was confirmed to be a 25 times improvement over the previous version. Using a single IA, ECG and PPG can be monitored in the form of separated ECG and PPG signals. In addition, for the first time, a merged ECG/PPG signal is acquired, which has features of both ECG and PPG peaks.

CONCEPTS OF ELECTRONICALLY-CONTROLLED ELECTROMECHANICAL/MECHANOELECTRICAL STEER-, AUTODRIVE- AND AUTOABSORBABLE WHEELS FOR ENVIRONMENTALLY-FRIENDLY TRI-MODE SUPERCARS

1994 ◽  
Vol 04 (04) ◽  
pp. 501-516 ◽  
Author(s):  
BOGDAN T. FIJALKOWSKI ◽  
JAN W. KROSNICKI
Keyword(s):  
Direct Current ◽  
Integrated Circuit ◽  
Environmentally Friendly ◽  
Alternating Current ◽  
Switching Frequency ◽  
Neuro Fuzzy ◽  
Interior Permanent Magnet ◽  
Application Specific Integrated Circuit ◽  
Computer Processor ◽  
Application Specific

Concepts of the electronically-controlled electromechanical/mechanoelectrical Steer-, Autodrive- and Autoabsorbable Wheels (SA2W) with their brushless Alternating Current-to-Alternating Current (AC-AC), Alternating Current-to-Direct Current-Alternating Current (AC-DC-AC) and/or Direct Current-to-Alternating Current (DC-AC)/Alternating Current-to-Direct Current (AC-DC) macroelectronic converter commutator (macro-commutator) wheel-hub motors/generators with the Application Specific Integrated Matrixer (ASIM) macroelectronic converter commutators (ASIM macrocommutators) and Application Specific Integrated Circuit (ASIC) microelectronic Neuro-Fuzzy (NF) computer (processor) controllers (ASIC NF microcontrollers) for environmentally-friendly tri-mode supercars (advanced ultralight hybrids) have been conceived by the first author and designed by both authors with the Cracow University of Technology’s Automotive Mechatronics Research and Development (R&D) Team. These electromechanical/mechanoelectrical wheel-hub motors/generators, respectively, for instance, can be composed of the outer rotor with the Interior Permanent Magnet (IPM) poles and the inner stator that has the three-phase armature winding. The macroelectronic converter commutator establishes the AC-AC cycloconverter, AC-DC rectifier-DC-AC inverter and/or DC-AC inverter/AC-DC rectifier ASIM macrocommutator. The microelectronic NF computer (processor) controller establishes the ASIC microcomputer-based NF microcontroller. By adopting continuous semiconductor bipolar electrical valves in the high-power ASIM, it has been able to increase the commutation (switching) frequency and reduce harmonic losses of the electromechanical/mechanoelectrical wheel-hub motors/generators, respectively.

High-Performance Reconfigurable Computing

2019 ◽  
pp. 731-744
Author(s):  
Mário Pereira Vestias
Keyword(s):  
Power Consumption ◽  
Integrated Circuit ◽  
Reconfigurable Computing ◽  
High Performance ◽  
General Purpose ◽  
Reconfigurable Hardware ◽  
Coarse Grained ◽  
Lower Power ◽  
Fine Grained ◽  
Application Specific

High-performance reconfigurable computing systems integrate reconfigurable technology in the computing architecture to improve performance. Besides performance, reconfigurable hardware devices also achieve lower power consumption compared to general-purpose processors. Better performance and lower power consumption could be achieved using application-specific integrated circuit (ASIC) technology. However, ASICs are not reconfigurable, turning them application specific. Reconfigurable logic becomes a major advantage when hardware flexibility permits to speed up whatever the application with the same hardware module. The first and most common devices utilized for reconfigurable computing are fine-grained FPGAs with a large hardware flexibility. To reduce the performance and area overhead associated with the reconfigurability, coarse-grained reconfigurable solutions has been proposed as a way to achieve better performance and lower power consumption. In this chapter, the authors provide a description of reconfigurable hardware for high-performance computing.

High-Performance Reconfigurable Computing

2018 ◽  
pp. 4018-4029
Author(s):  
Mário Pereira Vestias
Keyword(s):  
Power Consumption ◽  
Integrated Circuit ◽  
Reconfigurable Computing ◽  
High Performance ◽  
General Purpose ◽  
Reconfigurable Hardware ◽  
Coarse Grained ◽  
Lower Power ◽  
Fine Grained ◽  
Application Specific

High-Performance Reconfigurable Computing systems integrate reconfigurable technology in the computing architecture to improve performance. Besides performance, reconfigurable hardware devices also achieve lower power consumption compared to General-Purpose Processors. Better performance and lower power consumption could be achieved using Application Specific Integrated Circuit (ASIC) technology. However, ASICs are not reconfigurable, turning them application specific. Reconfigurable logic becomes a major advantage when hardware flexibility permits to speed up whatever the application with the same hardware module. The first and most common devices utilized for reconfigurable computing are fine-grained FPGAs with a large hardware flexibility. To reduce the performance and area overhead associated with the reconfigurability, coarse-grained reconfigurable solutions has been proposed as a way to achieve better performance and lower power consumption. In this chapter we will provide a description of reconfigurable hardware for high performance computing.

scholarly journals Dual tasking to optimize performance for the tactical athlete

Neurology ◽  
2018 ◽  
Vol 91 (23 Supplement 1) ◽  
pp. S21.2-S21
Author(s):  
Selena Bobula ◽  
Jami Skarda-Craft ◽  
Alina Souvignier
Keyword(s):  
Traumatic Brain Injury ◽  
Brain Injury ◽  
High Performance ◽  
Task Demands ◽  
Interdisciplinary Treatment ◽  
Service Members ◽  
Interdisciplinary Management ◽  
Language Fluency ◽  
Dual Tasking ◽  
High Level

This session with cover aspects of the DoD's Intrepid Spirit (IS) model for caring for service members with symptoms of traumatic brain injury (TBI) and comorbidities and taking care further with interdisciplinary management of the high-level functioning tactical athlete. Traumatic brain injury and concussion are common injuries among service members and athletes. As more research is completed on concussion, consequences of this injury have become better understood, but much is still left unknown, to include proper treatment for high performance tactical athletes and service members. This lecture will discuss interdisciplinary treatment for high-level performance needs with emphasis on utilization of dual tasking. This session will describe the IS mission and programs available through the Warrior Recovery Center at Fort Carson then further expand upon specialized co-treatments between Speech-Language Pathology (SLP) and Physical Therapy (PT) to push high-level patients to a higher standard. These interventions include aggressive dual-task demands with balance, exertional, and endurance tasks combined with challenges of working memory, delayed recall, visual tracking, language fluency, visual reasoning, and executive functions in English and the service member's secondary language. A case report will be provided to offer example interventions as well as improvements throughout treatment for service members who participated in this advanced intervention.

scholarly journals Design of ASIC Square Calculator Using AncientVedic Mathematics

2018 ◽  
Vol 7 (2.23) ◽  
pp. 464
Author(s):  
Angshuman Khan ◽  
Sudip Halder ◽  
Shubhajit Pal
Keyword(s):  
Integrated Circuit ◽  
Software Tool ◽  
Logic Gates ◽  
Digital Logic ◽  
Simple Design ◽  
Innovative Design ◽  
Circuit Asic ◽  
Vedic Mathematics ◽  
Application Specific Integrated Circuit ◽  
Application Specific

This article includes a simple design of Vedic square calculator for Application Specific Integrated Circuit (ASIC). This is a straightforward and innovative design of Vedic calculator using only few basic digital logic gates. Among the all sutras and sub sutras of ancient Vedic mathematics, the sutra ‘Urdhva Tiryagbyham’ is used here for square calculation of two bits numbers which results in an effortless and faster method of square calculation than all the existing methods. The design and minimization of the circuit has been carried out to achieve a standard architecture that is the simplest too. Here Xilinx ISE software tool is used rigorously to simulate the architecture.  

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