Application of Photoemission Microscopy and Focused Ion Beam Microsurgery to an Investigation of Latchup

Author(s):  
D.C. Mayer ◽  
R.J. Ferro ◽  
D.L. Leung ◽  
M.A. Dooley ◽  
J.R. Scarpulla

Abstract Radiation-induced latchup sites in a high-performance commercial application-specific integrated circuit (ASIC) manufactured in a bipolar gate array have been identified using a photoemission (PE) microscope before and after isolating individual circuit elements with a focused ion beam (FIB) system. Latchup sites were determined to be associated with grounded unused resistors and transistors in an emitter-coupled logic (ECL) input buffer. Simulation of the oxide isolation scheme confirmed the presence of pnpn structures at the likely latchup sites. A corrective action to redesign the layouts to disconnect unused resistors and transistors resulted in successful elimination of latchup in the ECL buffers.

Computers ◽  
2020 ◽  
Vol 9 (3) ◽  
pp. 70
Author(s):  
Carolina Fernández ◽  
Sergio Giménez ◽  
Eduard Grasa ◽  
Steve Bunch

The lack of high-performance RINA (Recursive InterNetwork Architecture) implementations to date makes it hard to experiment with RINA as an underlay networking fabric solution for different types of networks, and to assess RINA’s benefits in practice on scenarios with high traffic loads. High-performance router implementations typically require dedicated hardware support, such as FPGAs (Field Programmable Gate Arrays) or specialized ASICs (Application Specific Integrated Circuit). With the advance of hardware programmability in recent years, new possibilities unfold to prototype novel networking technologies. In particular, the use of the P4 programming language for programmable ASICs holds great promise for developing a RINA router. This paper details the design and part of the implementation of the first P4-based RINA interior router, which reuses the layer management components of the IRATI Linux-based RINA implementation and implements the data-transfer components using a P4 program. We also describe the configuration and testing of our initial deployment scenarios, using ancillary open-source tools such as the P4 reference test software switch (BMv2) or the P4Runtime API.


2018 ◽  
Author(s):  
Steve Wang ◽  
Jim McGinn ◽  
Peter Tvarozek ◽  
Amir Weiss

Abstract Secondary electron detector (SED) plays a vital role in a focused ion beam (FIB) system. A successful circuit edit requires a good effective detector. Novel approach is presented in this paper to improve the performance of such a detector, making circuit altering for the most advanced integrated circuit (IC) possible.


Author(s):  
Ching Shan Sung ◽  
Hsiu Ting Lee ◽  
Jian Shing Luo

Abstract Transmission electron microscopy (TEM) plays an important role in the structural analysis and characterization of materials for process evaluation and failure analysis in the integrated circuit (IC) industry as device shrinkage continues. It is well known that a high quality TEM sample is one of the keys which enables to facilitate successful TEM analysis. This paper demonstrates a few examples to show the tricks on positioning, protection deposition, sample dicing, and focused ion beam milling of the TEM sample preparation for advanced DRAMs. The micro-structures of the devices and samples architectures were observed by using cross sectional transmission electron microscopy, scanning electron microscopy, and optical microscopy. Following these tricks can help readers to prepare TEM samples with higher quality and efficiency.


Author(s):  
Romain Desplats ◽  
Timothee Dargnies ◽  
Jean-Christophe Courrege ◽  
Philippe Perdu ◽  
Jean-Louis Noullet

Abstract Focused Ion Beam (FIB) tools are widely used for Integrated Circuit (IC) debug and repair. With the increasing density of recent semiconductor devices, FIB operations are increasingly challenged, requiring access through 4 or more metal layers to reach a metal line of interest. In some cases, accessibility from the front side, through these metal layers, is so limited that backside FIB operations appear to be the most appropriate approach. The questions to be resolved before starting frontside or backside FIB operations on a device are: 1. Is it do-able, are the metal lines accessible? 2. What is the optimal positioning (e.g. accessing a metal 2 line is much faster and easier than digging down to a metal 6 line)? (for the backside) 3. What risk, time and cost are involved in FIB operations? In this paper, we will present a new approach, which allows the FIB user or designer to calculate the optimal FIB operation for debug and IC repair. It automatically selects the fastest and easiest milling and deposition FIB operations.


Author(s):  
Chin Kai Liu ◽  
Chi Jen. Chen ◽  
Jeh Yan.Chiou ◽  
David Su

Abstract Focused ion beam (FIB) has become a useful tool in the Integrated Circuit (IC) industry, It is playing an important role in Failure Analysis (FA), circuit repair and Transmission Electron Microscopy (TEM) specimen preparation. In particular, preparation of TEM samples using FIB has become popular within the last ten years [1]; the progress in this field is well documented. Given the usefulness of FIB, “Artifact” however is a very sensitive issue in TEM inspections. The ability to identify those artifacts in TEM analysis is an important as to understanding the significance of pictures In this paper, we will describe how to measure the damages introduced by FIB sample preparation and introduce a better way to prevent such kind of artifacts.


Author(s):  
K. N. Hooghan ◽  
K. S. Wills ◽  
P.A. Rodriguez ◽  
S.J. O’Connell

Abstract Device repair using Focused Ion Beam(FIB) systems has been in use for most of the last decade. Most of this has been done by people who have been essentially self-taught. The result has been a long learning curve to become proficient in device repair. Since a great deal of the problem is that documentation on this “art form” is found in papers from many different disciplines, this work attempts to summarize all of the available information under one title. The primary focus of FIB device repair is to ensure and maintain device integrity and subsequently retain market share while optimizing the use of the instrument, usually referred to as ‘beam time’. We describe and discuss several methods of optimizing beam time. First, beam time should be minimized while doing on chip navigation to reach the target areas. Several different approaches are discussed: dead reckoning, 3-point alignment, CAD-based navigation, and optical overlay. Second, after the repair areas are located and identified, the desired metal levels must be reached using a combination of beam currents and gas chemistries, and then filled up and strapped to make final connections. Third, cuts and cleanups must be performed as required for the final repair. We will discuss typical values of the beam currents required to maintain device integrity while concurrently optimizing repair time. Maintaining device integrity is difficult because of two potentially serious interactions of the FIB on the substrate: 1) since the beam consists of heavy metal ions (typically Gallium) the act of imaging the surface produces some physical damage; 2) the beam is positively charged and puts some charge into the substrate, making it necessary to use great care working in and around capacitors or active areas such as transistors, in order to avoid changing the threshold voltage of the devices. Strategies for minimizing potential damage and maximizing quality and throughput will be discussed.


Electronics ◽  
2021 ◽  
Vol 10 (6) ◽  
pp. 679
Author(s):  
Jongpal Kim

An instrumentation amplifier (IA) capable of sensing both voltage and current at the same time has been introduced and applied to electrocardiogram (ECG) and photoplethysmogram (PPG) measurements for cardiovascular health monitoring applications. The proposed IA can switch between the voltage and current sensing configurations in a time–division manner faster than the ECG and PPG bandwidths. The application-specific integrated circuit (ASIC) of the proposed circuit design was implemented using 180 nm CMOS fabrication technology. Input-referred voltage noise and current noise were measured as 3.9 µVrms and 172 pArms, respectively, and power consumption was measured as 34.9 µA. In the current sensing configuration, a current noise reduction technique is applied, which was confirmed to be a 25 times improvement over the previous version. Using a single IA, ECG and PPG can be monitored in the form of separated ECG and PPG signals. In addition, for the first time, a merged ECG/PPG signal is acquired, which has features of both ECG and PPG peaks.


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