Flip–flop selection for partial enhance scan chain using DTESFF for high transition delay fault coverage

2013 ◽  
Vol 4 (3) ◽  
pp. 303-311 ◽  
Author(s):  
Ashok Kumar Suhag ◽  
Vivek Shrivastava ◽  
Nidhi Singh
Keyword(s):  
Fault Coverage ◽  
Delay Fault ◽  
Flip Flop ◽  
High Transition ◽  
Selection For ◽  
Transition Delay ◽  
Scan Chain

Methods for improving transition delay fault coverage using broadside tests

2006 ◽  
Author(s):  
N. Devtaprasanna ◽  
A. Gunda ◽  
P. Krishnamurthy ◽  
S.M. Reddy ◽  
I. Pomeranz
Keyword(s):  
Fault Coverage ◽  
Delay Fault ◽  
Transition Delay

scholarly journals Layout-aware scan chain synthesis for improved path delay fault coverage

2005 ◽  
Vol 24 (7) ◽  
pp. 1104-1114 ◽  
Author(s):  
P. Gupta ◽  
A.B. Kahng ◽  
I.I. Mandoiu ◽  
P. Sharma
Keyword(s):  
Fault Coverage ◽  
Path Delay ◽  
Delay Fault ◽  
Path Delay Fault ◽  
Chain Synthesis ◽  
Scan Chain

A novel method of improving transition delay fault coverage using multiple scan enable signals

2006 ◽  
Author(s):  
N. Devtaprasanna ◽  
A. Gunda ◽  
P. Krishnamurthy ◽  
S.M. Reddy ◽  
I. Pomeranz
Keyword(s):  
Fault Coverage ◽  
Delay Fault ◽  
Multiple Scan ◽  
Novel Method ◽  
Transition Delay

Timing Sensitivity Analysis of Logical Nodes in Scan Design Integrated Circuits by Pulsed Diode Laser Stimulation

2008 ◽  
Author(s):  
T. Kiyan ◽  
C. Boit ◽  
C. Brillert
Keyword(s):  
Laser Pulse ◽  
Integrated Circuits ◽  
Continuous Wave ◽  
Fault Injection ◽  
Scan Design ◽  
Flip Flop ◽  
Laser Stimulation ◽  
Scan Chain ◽  
P Type ◽  
Scan Pattern

Abstract In this paper, a methodology based upon laser stimulation and a comparison of continuous wave and pulsed laser operation will be presented that localizes the fault relevant sites in a fully functional scan chain cell. The technique uses a laser incident from the backside to inject soft faults into internal nodes of a master-slave scan flip-flop in consequence of localized photocurrent. Depending on the illuminated type of the transistors (n- or p-type), injection of a logic ‘0’ or ‘1’ into the master or the slave stage of a flip-flop takes place. The laser pulse is externally triggered and can easily be shifted to various time slots in reference to clock and scan pattern. This feature of the laser diode allows triggering the laser pulse on the rising or the falling edge of the clock. Therefore, it is possible to choose the stage of the flip-flop in which the fault injection should occur. It is also demonstrated that the technique is able to identify the most sensitive signal condition for fault injection with a better time resolution than the pulse width of the laser, a significant improvement for failure analysis of integrated circuits.

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