Timing Sensitivity Analysis of Logical Nodes in Scan Design Integrated Circuits by Pulsed Diode Laser Stimulation

2008 ◽  
Author(s):  
T. Kiyan ◽  
C. Boit ◽  
C. Brillert
Keyword(s):  
Laser Pulse ◽  
Integrated Circuits ◽  
Continuous Wave ◽  
Fault Injection ◽  
Scan Design ◽  
Flip Flop ◽  
Laser Stimulation ◽  
Scan Chain ◽  
P Type ◽  
Scan Pattern

Abstract In this paper, a methodology based upon laser stimulation and a comparison of continuous wave and pulsed laser operation will be presented that localizes the fault relevant sites in a fully functional scan chain cell. The technique uses a laser incident from the backside to inject soft faults into internal nodes of a master-slave scan flip-flop in consequence of localized photocurrent. Depending on the illuminated type of the transistors (n- or p-type), injection of a logic ‘0’ or ‘1’ into the master or the slave stage of a flip-flop takes place. The laser pulse is externally triggered and can easily be shifted to various time slots in reference to clock and scan pattern. This feature of the laser diode allows triggering the laser pulse on the rising or the falling edge of the clock. Therefore, it is possible to choose the stage of the flip-flop in which the fault injection should occur. It is also demonstrated that the technique is able to identify the most sensitive signal condition for fault injection with a better time resolution than the pulse width of the laser, a significant improvement for failure analysis of integrated circuits.

Representative Scan Architecture

2016 ◽  
Vol 25 (05) ◽  
pp. 1650040
Author(s):  
Ling Zhang ◽  
Jishun Kuang
Keyword(s):  
Integrated Circuits ◽  
Test Data ◽  
Switching Activity ◽  
Hardware Cost ◽  
Test Power ◽  
Test Set ◽  
Flip Flop ◽  
Chain Architecture ◽  
Multiple Scan ◽  
Scan Chain

Test power is one of the most challenges faced by Integrated Circuits. The author proposes a general scan chain architecture called Representative Scan (RS). It transforms the scan cells of conventional scan chain or sub-chain into circular shift registers and a representative flip-flop is chosen for each circular shift register, these representative flip-flops are connected serially to setup into the RS architecture. Thus, test data shifting path is shortened, then the switching activity is reduced in the shifting operates. The proposed scan architecture has the similar test power with the multiple scan chain, and only needs same test pins with single scan chain without added test pins. The experimental results show that the proposed scan architecture achieves very low shifting power. For benchmark circuits of ISCAS89, the shifting power of the best architecture of RS is only 0.53%–13.59% of the conventional scan. Especially for S35932, the shifting power on mintest test set is only 0.53% of the corresponding conventional scan. Compared with the conventional scan, the RS only needs to add a multiplexer for each scan cells, and the hardware cost is not high.

Interface morphology of thermal oxide grown on polycrystalline silicon by different processes

1992 ◽  
Vol 50 (2) ◽  
pp. 1396-1397
Author(s):  
H. Yen ◽  
E. P. Kvam ◽  
R. Bashir ◽  
S. Venkatesan ◽  
G. W. Neudeck
Keyword(s):  
Integrated Circuits ◽  
Polycrystalline Silicon ◽  
Silicon Films ◽  
Interface Morphology ◽  
Oxide Interface ◽  
Poly Silicon ◽  
Thermal Oxide ◽  
Grain Orientations ◽  
Polycrystalline Silicon Films ◽  
P Type

Polycrystalline silicon, when highly doped, is commonly used in microelectronics applications such as gates and interconnects. The packing density of integrated circuits can be enhanced by fabricating multilevel polycrystalline silicon films separated by insulating SiO2 layers. It has been found that device performance and electrical properties are strongly affected by the interface morphology between polycrystalline silicon and SiO2. As a thermal oxide layer is grown, the poly silicon is consumed, and there is a volume expansion of the oxide relative to the atomic silicon. Roughness at the poly silicon/thermal oxide interface can be severely deleterious due to stresses induced by the volume change during oxidation. Further, grain orientations and grain boundaries may alter oxidation kinetics, which will also affect roughness, and thus stress.Three groups of polycrystalline silicon films were deposited by LPCVD after growing thermal oxide on p-type wafers. The films were doped with phosphorus or arsenic by three different methods.

Improving Yield Using Scan and DFT Based Analysis for High Performance PowerPC© Microprocessor

2006 ◽  
Author(s):  
Ray Talacka ◽  
Nandu Tendolkar ◽  
Cynthia Paquette
Keyword(s):  
High Performance ◽  
Yield Enhancement ◽  
Test Time ◽  
Balance Test ◽  
Specific Test ◽  
Defect Location ◽  
Test Methodology ◽  
Memory Arrays ◽  
Scan Chain ◽  
Scan Pattern

Abstract The use of memory arrays to drive yield enhancement has driven the development of many technologies. The uniformity of the arrays allows for easy testing and defect location. Unfortunately, the complexities of the logic circuitry are not represented well in the memory arrays. As technologies push to smaller geometries and the layout and timing of the logic circuitry become more problematic the ability to address yield issue is becoming critical. This paper presents the added yield enhancement capabilities of using e600 core Scan Chain and Scan Pattern testing for logic debug, ways to interpret the fail data, and test methodologies to balance test time and acquiring data. Selecting a specific test methodology and using today's advanced tools like Freescale's DFT/FA has been proven to find more yield issues, earlier, enabling quicker issue resolution.

scholarly journals Estimation and Analysis of Higher-Order Harmonics in Advanced Integrated Circuits to Implement Noise-Free Future-Generation Micro- and Nanoelectromechanical Systems

Micromachines ◽  
2021 ◽  
Vol 12 (5) ◽  
pp. 541
Author(s):  
Muhammad Imran Khan ◽  
Ahmed S. Alshammari ◽  
Badr M. Alshammari ◽  
Ahmed A. Alzamil
Keyword(s):  
Integrated Circuits ◽  
Frequency Band ◽  
Future Generation ◽  
Higher Order ◽  
Nanoelectromechanical Systems ◽  
Model Quality ◽  
Flip Flop ◽  
Transistor Model ◽  
Spectrum Generation ◽  
Time Fall

This work deals with the analysis of spectrum generation from advanced integrated circuits in order to better understand how to suppress the generation of high harmonics, especially in a given frequency band, to design and implement noise-free systems. At higher frequencies, the spectral components of signals with sharp edges contain more energy. However, current closed-form expressions have become increasingly unwieldy to compute higher-order harmonics. The study of spectrum generation provides an insight into suppressing higher-order harmonics (10th order and above), especially in a given frequency band. In this work, we discussed the influence of transistor model quality and input signal on estimates of the harmonic contents of switching waveforms. Accurate estimates of harmonic contents are essential in the design of highly integrated micro- and nanoelectromechanical systems. This paper provides a comparative analysis of various flip-flop/latch topologies on different process technologies, i.e., 130 and 65 nm. An FFT plot of the simulated results signifies that the steeper the spectrum roll-off, the lesser the content of higher-order harmonics. Furthermore, the results of the comparison illustrate the improvement in the rise time, fall time, clock-Q delay and spectrum roll-off on the better selection of slow-changing input signals and more accurate transistor models.

Low Power Pulse-Triggered Flip-Flop Based on Clock Triggering Edge Control Technique

2015 ◽  
Vol 24 (07) ◽  
pp. 1550094 ◽  
Author(s):  
Jizhong Shen ◽  
Liang Geng ◽  
Xuexiang Wu
Keyword(s):  
Integrated Circuits ◽  
Power Dissipation ◽  
Energy Efficient ◽  
Clock Cycle ◽  
Control Technique ◽  
Switching Activity ◽  
Digital Integrated Circuits ◽  
Flip Flop ◽  
Deep Impact ◽  
Power Pulse

Flip-flop is an important unit in digital integrated circuits, whose characteristics have a deep impact on the performance of the circuits. To reduce the power dissipation of flip-flops, clock triggering edge control technique is proposed, which is feasible to block one or two triggering edges of a clock cycle if they are redundant in dual-edge pulse-triggered flip-flops (DEPFFs). Based on this technique, redundant pulses can be suppressed when the input stays unchanged, and all the redundant triggerings are eliminated to reduce redundant transitions at the internal nodes of the flip-flop, so the power dissipation can be decreased. Then a novel DEPFF based on clock triggering edge control (DEPFF-CEC) technique is proposed. Based on the SMIC 65-nm technology, the post layout simulation results show that the proposed DEPFF-CEC gains an improvement of 8.03–39.83% in terms of power dissipation when the input switching activity is 10%, as compared with its counterparts. Thus, it is suitable for energy-efficient designs whose input data switching activity is low.

scholarly journals Efficient and Compact SR-flip Flop Optical Memory Based Photonic Crystals Platform

2021 ◽  
Author(s):  
Amr Hassan ◽  
Nihal F. F. Areed ◽  
Salah S. A. Obayya ◽  
Hamdi El Mikati
Keyword(s):  
Integrated Circuits ◽  
Optical Memory ◽  
Logic Gates ◽  
Power Input ◽  
Small Dimension ◽  
Square Lattice ◽  
Optical Logic ◽  
Flip Flop ◽  
Compact Size ◽  
Multiple Devices

Abstract The paper presents a different type of designing methods and operational improvements of the optical logic memory SR-flip flop (SR-FF). The proposed optical memory SR-FF is based on two optical NOR logic gates which use two-dimension (2D) photonic crystal (PhC) with a square lattice of silicon (Si) dielectric rods. The structure has a switching time in only a few Picoseconds with little power input and very little power loss. The proposed optical memory SR-FF has a small dimension 38x22 μm2 which makes it one of the best optimized and most practical structures to be used in all photonic integrated circuits (PICs). The ultra-compact size enables the possibility of multiple devices to be embedded in a single PIC chip.

Temperature Field of Repetitive Laser Pulse Irradiation and its Effect on Laser Surface Hardening

2011 ◽  
Vol 110-116 ◽  
pp. 823-830 ◽  
Author(s):  
Aniruddha Gupta ◽  
Ashish Kumar Nath
Keyword(s):  
Laser Pulse ◽  
Surface Hardening ◽  
Continuous Wave ◽  
High Carbon Steel ◽  
Laser Pulses ◽  
Phase Transformation Temperature ◽  
Continuous Wave Laser ◽  
Pulse Irradiation ◽  
Soaking Time ◽  
Analytical Expressions

Analytical expressions for the temperature rise in a semi-infinite workpiece due to the heating with CW and repetitive laser pulse irradiation have been derived. It has been shown that the soaking time at a temperature above the phase transformation temperature, on which the homogeneity of microstructure and the depth of hardening depend, can be increased by heating with repetitive laser pulses. Experimental results of surface hardening of high-carbon steel with repetitive laser pulses showed higher depth of hardening and better microstructure homogeneity compared to those with continuous wave laser.

Yield and Failure Analysis of FinFET Source to Drain Leakage in 12nm Technology

2020 ◽  
Author(s):  
Felix Beaudoin ◽  
Satish Kodali ◽  
Rohan Deshpande ◽  
Wayne Zhao ◽  
Edmund Banghart ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Fault Localization ◽  
Detailed Characterization ◽  
Laser Stimulation ◽  
Emission Microscopy ◽  
Scan Chain ◽  
Multiple Samples ◽  
Tem Lamella ◽  
Diffusion Activation

Abstract Fault localization using both dynamic laser stimulation and emission microscopy was used to localize the failing transistors within the failing scan chain latch on multiple samples. Nanoprobing was then performed and the source to drain leakage in N-type FinFETs was identified. After extensive detailed characterization, it was concluded that the N-type dopant signal was likely due to projections from the source/drain regions included in the TEM lamella. Datamining identified the scan chain fail to be occurring uniquely for a specific family of tools used during source/drain implant diffusion activation. This paper discusses the processes involved in yield delta datamining of FinFET and its advantages over failure characterization, fault localization, nanoprobing, and physical failure analysis.

Electro-Optical Probing for Capturing Fast-to-Rise Scan Chain Failures

2021 ◽  
Author(s):  
Karl Villareal ◽  
Rommel Estores ◽  
Peter Baert
Keyword(s):  
Fault Isolation ◽  
Flip Flop ◽  
Diagnosis System ◽  
Chain Analysis ◽  
System 2 ◽  
Optical Probing ◽  
Scan Chain ◽  
Imaging Sensor ◽  
Chain Links ◽  
Long Chain

Abstract The paper discusses an imaging sensor exhibiting a fast-to-rise sanity check failure from a scan chain test. The DUT was prepared for backside analysis in a portable daughter-card [1] that enabled the analyst to easily shift between testing platforms such as a standard imaging tester bench and compact scan diagnosis system [2], while being inspected under the Electro-Optical Probing (EOP) machine. To find a failing flip-flop in several-thousands long chain, broken scan chain analysis was performed to narrow down the search to a few chain links was implemented. EOP methods of fault isolation were employed to verify the location of the broken scan cell in those selected flip-flops. Finally, parallel lapping was done to confirm the location of the failing flip-flop under a SEM.

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