ESCALATION: Leveraging Logic Masking to Facilitate Path-Delay-Based Hardware Trojan Detection Methods

2018 ◽  
Vol 2 (1) ◽  
pp. 83-96 ◽  
Author(s):  
Arash Nejat ◽  
David Hely ◽  
Vincent Beroulle
2018 ◽  
Vol 14 (3) ◽  
pp. 1-23 ◽  
Author(s):  
Xiaotong Cui ◽  
Elnaz Koopahi ◽  
Kaijie Wu ◽  
Ramesh Karri

2014 ◽  
Vol 716-717 ◽  
pp. 1382-1386
Author(s):  
Da Xiao ◽  
Yue Fei Zhu ◽  
Sheng Li Liu ◽  
Dong Xia Wang ◽  
You Qiang Luo

This article selects HOL theorem proving systems for hardware Trojan detection and gives the symbol and meaning of theorem proving systems, and then introduces the symbol table, item and the meaning of HOL theorem proving systems. In order to solve the theorem proving the application of the system in hardware Trojan detection requirements, this article analyses basic hardware Trojan detection methods which applies for theorem proving systems and introduces the implementation methods and process of theorem proving about hardware Trojan detection.


Author(s):  
Shathanaa Rajmohan ◽  
N. Ramasubramanian ◽  
Nagi Naganathan

In past years, software used to be the main concern of computer security, and the hardware was assumed to be safe. However, Hardware Trojans, which are a malicious alteration to the circuit, pose a threat to the security of a system. Trojans may be distributed across different components of the system and can bring down the security by communicating with each other. Redundancy and vendor diversity-based methods exist to detect Hardware Trojans, but with an increase in the hardware overhead. This work proposes a novel vendor allocation procedure to reduce the hardware cost that comes with Trojan detection methods. To further reduce the cost by minimizing resource requirements, an evolutionary algorithm-based Design Space Exploration methodology is proposed with options for loop unrolling and operation chaining. For reducing the cost of hardware Trojan detection and isolation, the proposed algorithm extends an existing implementation of Firefly algorithm. The proposed method is compared with the existing algorithms, using cost-based and Pareto-based evaluations. The results obtained demonstrate the ability of the new algorithm in achieving better solutions with a 77% reduction in cost when compared to the previous solutions.


2018 ◽  
Vol 27 (09) ◽  
pp. 1850138 ◽  
Author(s):  
Atieh Amelian ◽  
Shahram Etemadi Borujeni

Hardware Trojan Horses (HTHs) are malicious modifications inserted in Integrated Circuit during fabrication steps. The HTHs are very small and can cause damages in circuit function. They cannot be detected by conventional testing methods. Due to dangerous effects of them, Hardware Trojan Detection has become a major concern in hardware security. In this paper, a new HTH detection method is presented based on side-channel analysis that uses path delay measurement. In this method, we find and observe the paths that Trojans have most effect on them. Most of the previous works add some structures to the circuit and need a large overhead cost. But, in our method, there is no modification in the circuit and we can use it for testing the circuits received after fabrication. The proposed method is evaluated with Xilinx FPGA over a number of test circuits. The results show that measuring the delays on 20 paths with an accuracy of 0.01[Formula: see text]ns can detect more than 80% of Trojans.


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