Design Space Exploration for Reducing Cost of Hardware Trojan Detection and Isolation during Architectural Synthesis

2020 ◽  
pp. 2150156
Author(s):  
Shathanaa Rajmohan ◽  
N. Ramasubramanian ◽  
Nagi Naganathan
Keyword(s):  
Design Space Exploration ◽  
Design Space ◽  
Space Exploration ◽  
Detection Methods ◽  
Main Concern ◽  
Hardware Trojan ◽  
Hardware Trojans ◽  
Hardware Trojan Detection ◽  
Trojan Detection ◽  
The Cost

In past years, software used to be the main concern of computer security, and the hardware was assumed to be safe. However, Hardware Trojans, which are a malicious alteration to the circuit, pose a threat to the security of a system. Trojans may be distributed across different components of the system and can bring down the security by communicating with each other. Redundancy and vendor diversity-based methods exist to detect Hardware Trojans, but with an increase in the hardware overhead. This work proposes a novel vendor allocation procedure to reduce the hardware cost that comes with Trojan detection methods. To further reduce the cost by minimizing resource requirements, an evolutionary algorithm-based Design Space Exploration methodology is proposed with options for loop unrolling and operation chaining. For reducing the cost of hardware Trojan detection and isolation, the proposed algorithm extends an existing implementation of Firefly algorithm. The proposed method is compared with the existing algorithms, using cost-based and Pareto-based evaluations. The results obtained demonstrate the ability of the new algorithm in achieving better solutions with a 77% reduction in cost when compared to the previous solutions.

scholarly journals Execution time - area tradeoff in gausing residual load decoder: Integrated exploration of chaining based schedule and allocation in HLS for hardware accelerators

2014 ◽  
Vol 27 (2) ◽  
pp. 235-249 ◽  
Author(s):  
Anirban Sengupta ◽  
Reza Sedaghat ◽  
Vipul Mishra
Keyword(s):  
Execution Time ◽  
Design Space Exploration ◽  
Design Space ◽  
Space Exploration ◽  
Integrated Design ◽  
Hardware Accelerators ◽  
Average Improvement ◽  
Genetic Algorithm Approach ◽  
High Level ◽  
The Cost

Design space exploration is an indispensable segment of High Level Synthesis (HLS) design of hardware accelerators. This paper presents a novel technique for Area-Execution time tradeoff using residual load decoding heuristics in genetic algorithms (GA) for integrated design space exploration (DSE) of scheduling and allocation. This approach is also able to resolve issues encountered during DSE of data paths for hardware accelerators, such as accuracy of the solution found, as well as the total exploration time during the process. The integrated solution found by the proposed approach satisfies the user specified constraints of hardware area and total execution time (not just latency), while at the same time offers a twofold unified solution of chaining based schedule and allocation. The cost function proposed in the genetic algorithm approach takes into account the functional units, multiplexers and demultiplexers needed during implementation. The proposed exploration system (ExpSys) was tested on a large number of benchmarks drawn from the literature for assessment of its efficiency. Results indicate an average improvement in Quality of Results (QoR) greater than 26% when compared to a recent well known GA based exploration method.

scholarly journals Think Smart, Play Dumb: Analyzing Deception in Hardware Trojan Detection Using Game Theory

2020 ◽  
Author(s):  
Tapadhir Das
Keyword(s):  
Integrated Circuits ◽  
Repeated Game ◽  
Third Party ◽  
Hardware Trojan ◽  
Hardware Trojans ◽  
Learning Stage ◽  
Hardware Trojan Detection ◽  
Trojan Detection ◽  
Utility Gain ◽  
Game Theoretic

In recent years, integrated circuits (ICs) have become<br>significant for various industries and their security has<br>been given greater priority, specifically in the supply chain.<br>Budgetary constraints have compelled IC designers to offshore manufacturing to third-party companies. When the designer gets the manufactured ICs back, it is imperative to test for potential threats like hardware trojans (HT). In this paper, a novel multilevel game-theoretic framework is introduced to analyze the interactions between a malicious IC manufacturer and the tester. In particular, the game is formulated as a non-cooperative, zerosum, repeated game using prospect theory (PT) that captures different players’ rationalities under uncertainty. The repeated game is separated into a learning stage, in which the defender<br><div>learns about the attacker’s tendencies, and an actual game stage, where this learning is used. Experiments show great incentive for the attacker to deceive the defender about their actual rationality by “playing dumb” in the learning stage (deception). This scenario is captured using hypergame theory to model the attacker’s view of the game. The optimal deception rationality of the attacker is analytically derived to maximize utility gain. For the defender, a first-step deception mitigation process is proposed to thwart the effects of deception. Simulation results show that the attacker can profit from the deception as it can successfully insert HTs in the manufactured ICs without being detected.</div><div><br></div><div>This paper has been accepted for publication in <b>IEEE Cyber Science Conference 2020</b><br></div>

Digital Hardware Design Formal Verification Based on HOL System

2014 ◽  
Vol 716-717 ◽  
pp. 1382-1386
Author(s):  
Da Xiao ◽  
Yue Fei Zhu ◽  
Sheng Li Liu ◽  
Dong Xia Wang ◽  
You Qiang Luo
Keyword(s):  
Formal Verification ◽  
Theorem Proving ◽  
Hardware Design ◽  
Detection Methods ◽  
Hardware Trojan ◽  
Symbol Table ◽  
Hardware Trojan Detection ◽  
Trojan Detection ◽  
Digital Hardware

This article selects HOL theorem proving systems for hardware Trojan detection and gives the symbol and meaning of theorem proving systems, and then introduces the symbol table, item and the meaning of HOL theorem proving systems. In order to solve the theorem proving the application of the system in hardware Trojan detection requirements, this article analyses basic hardware Trojan detection methods which applies for theorem proving systems and introduces the implementation methods and process of theorem proving about hardware Trojan detection.

scholarly journals Think Smart, Play Dumb: Analyzing Deception in Hardware Trojan Detection Using Game Theory

2020 ◽  
Author(s):  
Tapadhir Das ◽  
AbdelRahman Eldosouky ◽  
Shamik Sengupta
Keyword(s):  
Integrated Circuits ◽  
Repeated Game ◽  
Third Party ◽  
Hardware Trojan ◽  
Hardware Trojans ◽  
Learning Stage ◽  
Hardware Trojan Detection ◽  
Trojan Detection ◽  
Utility Gain ◽  
Game Theoretic

In recent years, integrated circuits (ICs) have become<br>significant for various industries and their security has<br>been given greater priority, specifically in the supply chain.<br>Budgetary constraints have compelled IC designers to offshore manufacturing to third-party companies. When the designer gets the manufactured ICs back, it is imperative to test for potential threats like hardware trojans (HT). In this paper, a novel multilevel game-theoretic framework is introduced to analyze the interactions between a malicious IC manufacturer and the tester. In particular, the game is formulated as a non-cooperative, zerosum, repeated game using prospect theory (PT) that captures different players’ rationalities under uncertainty. The repeated game is separated into a learning stage, in which the defender<br><div>learns about the attacker’s tendencies, and an actual game stage, where this learning is used. Experiments show great incentive for the attacker to deceive the defender about their actual rationality by “playing dumb” in the learning stage (deception). This scenario is captured using hypergame theory to model the attacker’s view of the game. The optimal deception rationality of the attacker is analytically derived to maximize utility gain. For the defender, a first-step deception mitigation process is proposed to thwart the effects of deception. Simulation results show that the attacker can profit from the deception as it can successfully insert HTs in the manufactured ICs without being detected.</div><div><br></div><div>This paper has been accepted for publication in <b>IEEE Cyber Science Conference 2020</b><br></div>

scholarly journals Think Smart, Play Dumb: Analyzing Deception in Hardware Trojan Detection Using Game Theory

2020 ◽  
Author(s):  
Tapadhir Das ◽  
AbdelRahman Eldosouky ◽  
Shamik Sengupta
Keyword(s):  
Integrated Circuits ◽  
Repeated Game ◽  
Third Party ◽  
Hardware Trojan ◽  
Hardware Trojans ◽  
Learning Stage ◽  
Hardware Trojan Detection ◽  
Trojan Detection ◽  
Utility Gain ◽  
Game Theoretic

In recent years, integrated circuits (ICs) have become<br>significant for various industries and their security has<br>been given greater priority, specifically in the supply chain.<br>Budgetary constraints have compelled IC designers to offshore manufacturing to third-party companies. When the designer gets the manufactured ICs back, it is imperative to test for potential threats like hardware trojans (HT). In this paper, a novel multilevel game-theoretic framework is introduced to analyze the interactions between a malicious IC manufacturer and the tester. In particular, the game is formulated as a non-cooperative, zerosum, repeated game using prospect theory (PT) that captures different players’ rationalities under uncertainty. The repeated game is separated into a learning stage, in which the defender<br><div>learns about the attacker’s tendencies, and an actual game stage, where this learning is used. Experiments show great incentive for the attacker to deceive the defender about their actual rationality by “playing dumb” in the learning stage (deception). This scenario is captured using hypergame theory to model the attacker’s view of the game. The optimal deception rationality of the attacker is analytically derived to maximize utility gain. For the defender, a first-step deception mitigation process is proposed to thwart the effects of deception. Simulation results show that the attacker can profit from the deception as it can successfully insert HTs in the manufactured ICs without being detected.</div><div><br></div><div>This paper has been accepted for publication in <b>IEEE Cyber Science Conference 2020</b><br></div>

scholarly journals A machine-learning-based hardware-Trojan detection approach for chips in the Internet of Things

2019 ◽  
Vol 15 (12) ◽  
pp. 155014771988809 ◽  
Author(s):  
Chen Dong ◽  
Jinghui Chen ◽  
Wenzhong Guo ◽  
Jian Zou
Keyword(s):  
Machine Learning ◽  
Internet Of Things ◽  
Detection Methods ◽  
Gradient Boosting ◽  
The Internet ◽  
Hardware Trojan ◽  
Hardware Trojan Detection ◽  
Trojan Detection ◽  
Extreme Gradient Boosting ◽  
The Internet Of Things

With the development of the Internet of Things, smart devices are widely used. Hardware security is one key issue in the security of the Internet of Things. As the core component of the hardware, the integrated circuit must be taken seriously with its security. The pre-silicon detection methods do not require gold chips, are not affected by process noise, and are suitable for the safe detection of a very large-scale integration. Therefore, more and more researchers are paying attention to the pre-silicon detection method. In this study, we propose a machine-learning-based hardware-Trojan detection method at the gate level. First, we put forward new Trojan-net features. After that, we use the scoring mechanism of the eXtreme Gradient Boosting to set up a new effective feature set of 49 out of 56 features. Finally, the hardware-Trojan classifier was trained and detected based on the new feature set by the eXtreme Gradient Boosting algorithm, respectively. The experimental results show that the proposed method can obtain 89.84% average Recall, 86.75% average F-measure, and 99.83% average Accuracy, which is the best detection result among existing machine-learning-based hardware-Trojan detection methods.

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