Fault tolerance of the star graph interconnection network

1994 ◽  
Vol 49 (3) ◽  
pp. 145-150 ◽  
Author(s):  
Zoran Jovanović ◽  
Jelena Mišić
Keyword(s):  
Fault Tolerance ◽  
Interconnection Network ◽  
Star Graph

The Generalized Connectivity of Bubble-Sort Star Graphs

2019 ◽  
Vol 30 (05) ◽  
pp. 793-809
Author(s):  
Shu-Li Zhao ◽  
Rong-Xia Hao
Keyword(s):  
Fault Tolerance ◽  
Upper Bound ◽  
Interconnection Networks ◽  
Interconnection Network ◽  
Star Graph ◽  
Important Indicator ◽  
Star Graphs ◽  
Generalized Connectivity ◽  
Internally Disjoint Trees

The connectivity plays an important role in measuring the fault tolerance and reliability of interconnection networks. The generalized [Formula: see text]-connectivity of a graph [Formula: see text], denoted by [Formula: see text], is an important indicator of a network’s ability for fault tolerance and reliability. The bubble-sort star graph, denoted by [Formula: see text], is a well known interconnection network. In this paper, we show that [Formula: see text] for [Formula: see text], that is, for any three vertices in [Formula: see text], there exist [Formula: see text] internally disjoint trees connecting them in [Formula: see text] for [Formula: see text], which attains the upper bound of [Formula: see text] given by Li et al. for [Formula: see text].

Reliability Analysis of the Generalized Exchanged Hypercube

2020 ◽  
Vol 30 (02) ◽  
pp. 2050009
Author(s):  
Qifan Zhang ◽  
Liqiong Xu ◽  
Weihua Yang ◽  
Shanshan Yin
Keyword(s):  
Fault Tolerance ◽  
Reliability Analysis ◽  
Network Structure ◽  
Complete Graph ◽  
Interconnection Network ◽  
Natural Extension ◽  
Graph Model ◽  
Text Component ◽  
Optimal Formula

Let [Formula: see text] be a non-complete graph, a subset [Formula: see text] is called a [Formula: see text]-component cut of [Formula: see text], if [Formula: see text] is disconnected and has at least [Formula: see text] components. The cardinality of the minimum [Formula: see text]-component cut is the [Formula: see text]-component connectivity of [Formula: see text] and is denoted by [Formula: see text]. The [Formula: see text]-component connectivity is a natural extension of the classical connectivity. As an application, the [Formula: see text]-component connectivity can be used to evaluate the reliability and fault tolerance of an interconnection network structure based on a graph model. In a previous work, E. Cheng et al. obtained the [Formula: see text]-component connectivity of the generalized exchanged hypercube [Formula: see text] for [Formula: see text] and [Formula: see text]. In this paper, we continue the work and determine that [Formula: see text] for [Formula: see text]. Moreover, we show that every optimal [Formula: see text]-component cut of [Formula: see text] is trivial for [Formula: see text] and [Formula: see text].

Component Edge Connectivity of Hypercubes

2018 ◽  
Vol 29 (06) ◽  
pp. 995-1001 ◽  
Author(s):  
Shuli Zhao ◽  
Weihua Yang ◽  
Shurong Zhang ◽  
Liqiong Xu
Keyword(s):  
Fault Tolerance ◽  
Complete Graph ◽  
Interconnection Networks ◽  
Interconnection Network ◽  
Optimal Solutions ◽  
Edge Connectivity ◽  
Important Measure ◽  
Minimum Number ◽  
Text Component

Fault tolerance is an important issue in interconnection networks, and the traditional edge connectivity is an important measure to evaluate the robustness of an interconnection network. The component edge connectivity is a generalization of the traditional edge connectivity. The [Formula: see text]-component edge connectivity [Formula: see text] of a non-complete graph [Formula: see text] is the minimum number of edges whose deletion results in a graph with at least [Formula: see text] components. Let [Formula: see text] be an integer and [Formula: see text] be the decomposition of [Formula: see text] such that [Formula: see text] and [Formula: see text] for [Formula: see text]. In this note, we determine the [Formula: see text]-component edge connectivity of the hypercube [Formula: see text], [Formula: see text] for [Formula: see text]. Moreover, we classify the corresponding optimal solutions.

A Note of Independent Number and Domination Number of Qn,k,m-Graph

2019 ◽  
Vol 29 (03) ◽  
pp. 1950011
Author(s):  
Jiafei Liu ◽  
Shuming Zhou ◽  
Zhendong Gu ◽  
Yihong Wang ◽  
Qianru Zhou
Keyword(s):  
Interconnection Networks ◽  
Interconnection Network ◽  
Domination Number ◽  
Multiprocessor System ◽  
Star Graph ◽  
Minimum Cardinality ◽  
Arrangement Graph ◽  
Independent Number ◽  
Potential Applications ◽  
By Products

The independent number and domination number are two essential parameters to assess the resilience of the interconnection network of multiprocessor systems which is usually modeled by a graph. The independent number, denoted by [Formula: see text], of a graph [Formula: see text] is the maximum cardinality of any subset [Formula: see text] such that no two elements in [Formula: see text] are adjacent in [Formula: see text]. The domination number, denoted by [Formula: see text], of a graph [Formula: see text] is the minimum cardinality of any subset [Formula: see text] such that every vertex in [Formula: see text] is either in [Formula: see text] or adjacent to an element of [Formula: see text]. But so far, determining the independent number and domination number of a graph is still an NPC problem. Therefore, it is of utmost importance to determine the number of independent and domination number of some special networks with potential applications in multiprocessor system. In this paper, we firstly resolve the exact values of independent number and upper and lower bound of domination number of the [Formula: see text]-graph, a common generalization of various popular interconnection networks. Besides, as by-products, we derive the independent number and domination number of [Formula: see text]-star graph [Formula: see text], [Formula: see text]-arrangement graph [Formula: see text], as well as three special graphs.

A RECONFIGURATION TECHNIQUE FOR RELIABLE VLSI DSP ARRAY PROCESSORS

1992 ◽  
Vol 02 (03) ◽  
pp. 281-304
Author(s):  
SANJAY P. POPLI ◽  
MAGDY A. BAYOUMI ◽  
AKASH TYAGI
Keyword(s):  
Fault Tolerance ◽  
Error Detection ◽  
High Performance ◽  
Interconnection Network ◽  
Digital Signal ◽  
Design Criterion ◽  
Fault Detection And Diagnosis ◽  
Detection Technique ◽  
Concurrent Error Detection ◽  
Tolerance Strategy

Real-time digital signal processing (DSP) applications require high performance parallel architectures that are also reliable. VLSI arrays are good candidates for providing the required high throughput for these applications. These arrays which consist of a number of regularly interconnected processing elements (PEs) will not function correctly in the presence of even a single fault in any of the PEs. Fault tolerance has therefore become a vital design criterion for VLSI arrays. In this paper, a fault tolerance strategy for VLSI arrays is proposed, which significantly improves the reliability of the system. The fault tolerance scheme is composed of two phases: testing and locating faults (fault detection and diagnosis), and reconfiguration. The first phase employs an on-line error detection technique which achieves a compromise between the space and time redundancy approaches. This concurrent error detection technique reduces the rollback time considerably. The reconfiguration phase is achieved by using a global control responsible for changing the states of the switches in the interconnection network. Backtracking is introduced into the algorithm for maximizing the processor utilization, at the same time keeping the complexity of the interconnection network as simple as possible. Finally, a reliability analysis of this scheme using a Markov model and a comparison with some previous schemes are given.

Designing a New Class of Fault Tolerant Multistage Interconnection Networks

2005 ◽  
Vol 06 (04) ◽  
pp. 361-382 ◽  
Author(s):  
K. V. Arya ◽  
R. K. Ghosh
Keyword(s):  
Fault Tolerance ◽  
Interconnection Networks ◽  
Fault Tolerant ◽  
Interconnection Network ◽  
Multistage Interconnection Networks ◽  
Multistage Interconnection Network ◽  
New Class

This paper proposes a technique to modify a Multistage Interconnection Network (MIN) to augment it with fault tolerant capabilities. The augmented MIN is referred to as Enhanced MIN (E-MIN). The technique employed for construction of E-MIN is compared with the two known physical fault tolerance techniques, namely, extra staging and chaining. EMINs are found to be more generic than extra staged networks and less expensive than chained networks. The EMIN realizes all the permutations realizable by the original MIN. The routing strategies under faulty and fault free conditions are shown to be very simple in the case of E-MINs.

Sign in / Sign up

Export Citation Format

Share Document