Encoding Techniques for On-Chip Communication Architectures

2008 ◽  
pp. 253-300 ◽  
Author(s):  
Sudeep Pasricha ◽  
Nikil Dutt
Keyword(s):  
Communication Architectures ◽  
On Chip

scholarly journals A New Router Architecture for High-Performance Intrachip Networks

2008 ◽  
Vol 3 (1) ◽  
pp. 23-31
Author(s):  
Everton Carara ◽  
Ney Calazans ◽  
Fernando Moraes
Keyword(s):  
High Performance ◽  
Packet Switching ◽  
Circuit Switching ◽  
Transmission Method ◽  
Communication Architecture ◽  
Virtual Channels ◽  
Trade Offs ◽  
Communication Architectures ◽  
Session Layer ◽  
On Chip

For almost a decade now, Network on Chip (NoC) concepts have evolved to provide an interesting alternative to more traditional intrachip communication architectures (e.g. shared busses) for the design of complex Systems on Chip (SoCs). A considerable number of NoC proposals are available, focusing on different sets of optimization aspects, related to specific classes of applications. Each such application employs a NoC as part of its underlying implementation infrastructure. Many of the mentioned optimization aspects target results such as Quality of Service (QoS) achievement and/or power consumption reduction. On the other hand, the use of NoCs brings about the solution of new design problems, such to the choice of synchronization method to employ between NoC routers and application modules mapping. Although the availability of NoC structures is already rather ample, some design choices are at base of many, if not most, NoC proposals. These include the use of wormhole packet switching and virtual channels. This work pledges against this practice. It discusses trade-offs of using circuit or packet switching, arguing in favor the use of the former with fixed size packets (cells). Quantitative data supports the argumentation. Also, the work proposes and justifies replacing the use of virtual channels by replicated channels, based on the abundance of wires in current and expected deep sub-micron technologies. Finally, the work proposes a transmission method coupling the use of session layer structures to circuit switching to better support application implementation. The main reported result is the availability of a router with reduced latency and area, a communication architecture adapted for high-performance applications.

System-Level Analysis of MPSoCs with a Hardware Scheduler

2014 ◽  
pp. 335-367
Author(s):  
Diandian Zhang ◽  
Jeronimo Castrillon ◽  
Stefan Schürmans ◽  
Gerd Ascheid ◽  
Rainer Leupers ◽  
...  
Keyword(s):  
Resource Management ◽  
Distributed Memory ◽  
Point Of View ◽  
System Level ◽  
Video Decoder ◽  
Communication Architecture ◽  
Communication Architectures ◽  
Runtime Management ◽  
On Chip ◽  
Ip Blocks

Efficient runtime resource management in heterogeneous Multi-Processor Systems-on-Chip (MPSoCs) for achieving high performance and energy efficiency is one key challenge for system designers. In the past years, several IP blocks have been proposed that implement system-wide runtime task and resource management. As the processor count continues to increase, it is important to analyze the scalability of runtime managers at the system-level for different communication architectures. In this chapter, the authors analyze the scalability of an Application-Specific Instruction-Set Processor (ASIP) for runtime management called OSIP on two platform paradigms: shared and distributed memory. For the former, a generic bus is used as interconnect. For distributed memory, a Network-on-Chip (NoC) is used. The effects of OSIP and the communication architecture are jointly investigated from the system point of view, based on a broad case study with real applications (an H.264 video decoder and a digital receiver for wireless communications) and a synthetic benchmark application.

scholarly journals Modeling and Simulation of Network-on-Chip Systems with DEVS and DEUS

2014 ◽  
Vol 2014 ◽  
pp. 1-9 ◽  
Author(s):  
Michele Amoretti
Keyword(s):  
Modeling And Simulation ◽  
Discrete Event ◽  
General Purpose ◽  
System Specification ◽  
Modeling Framework ◽  
Steep Learning Curve ◽  
Networks On Chip ◽  
Systems On Chip ◽  
Communication Architectures ◽  
On Chip

Networks on-chip (NoCs) provide enhanced performance, scalability, modularity, and design productivity as compared with previous communication architectures for VLSI systems on-chip (SoCs), such as buses and dedicated signal wires. Since the NoC design space is very large and high dimensional, evaluation methodologies rely heavily on analytical modeling and simulation. Unfortunately, there is no standard modeling framework. In this paper we illustrate how to design and evaluate NoCs by integrating the Discrete Event System Specification (DEVS) modeling framework and the simulation environment called DEUS. The advantage of such an approach is that both DEVS and DEUS support modularity—the former being a sound and complete modeling framework and the latter being an open, general-purpose platform, characterized by a steep learning curve and the possibility to simulate any system at any level of detail.

scholarly journals Applying Partial Power-Gating to Direction-Sliced Network-on-Chip

2015 ◽  
Vol 2015 ◽  
pp. 1-16 ◽  
Author(s):  
Feng Wang ◽  
Xiantuo Tang ◽  
Zuocheng Xing
Keyword(s):  
Power Efficiency ◽  
Network Performance ◽  
Routing Algorithm ◽  
Network On Chip ◽  
Leakage Power ◽  
Power Gating ◽  
Load Range ◽  
Communication Architectures ◽  
On Chip ◽  
Many Core

Network-on-Chip (NoC) is one of critical communication architectures for future many-core systems. As technology is continually scaling down, on-chip network meets the increasing leakage power crisis. As a leakage power mitigation technique, power-gating can be utilized in on-chip network to solve the crisis. However, the network performance is severely affected by the disconnection in the conventional power-gated NoC. In this paper, we propose a novel partial power-gating approach to improve the performance in the power-gated NoC. The approach mainly involves a direction-slicing scheme, an improved routing algorithm, and a deadlock recovery mechanism. In the synthetic traffic simulation, the proposed design shows favorable power-efficiency at low-load range and achieves better performance than the conventional power-gated one. For the application trace simulation, the design in the mesh/torus network consumes 15.2%/18.9% more power on average, whereas it can averagely obtain 45.0%/28.7% performance improvement compared with the conventional power-gated design. On balance, the proposed design with partial power-gating has a better tradeoff between performance and power-efficiency.

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