Verification and Security Issues in On-Chip Communication Architecture Design

2008 ◽  
pp. 367-402
Author(s):  
Sudeep Pasricha ◽  
Nikil Dutt
Keyword(s):  
Architecture Design ◽  
Communication Architecture ◽  
Security Issues ◽  
On Chip

PMCNOC: A Pipelining Multi-channel Central Caching Network-on-chip Communication Architecture Design

2009 ◽  
Vol 60 (3) ◽  
pp. 315-331 ◽  
Author(s):  
N. Wang ◽  
A. Sanusi ◽  
P. Y. Zhao ◽  
M. Elgamel ◽  
M. A. Bayoumi
Keyword(s):  
Network On Chip ◽  
Architecture Design ◽  
Communication Architecture ◽  
On Chip

Internet of Things (IoT): Classification, Secured Architecture Based on Data Sensitivity, Security Issues and Their Countermeasures

2021 ◽  
Vol 20 (Supp01) ◽  
pp. 2140001
Author(s):  
Bremnavas Ismail Mohideen ◽  
Basem Assiri
Keyword(s):  
Internet Of Things ◽  
Pervasive Computing ◽  
Architecture Design ◽  
Iot Security ◽  
Significant Development ◽  
Security Issues ◽  
Physical Resources ◽  
Healthcare Monitoring ◽  
Data Sensitivity

In recent decades, the communication of electronic equipment and physical resources is combined. Internet of Things (IoT) distributes things widely in the network. The IoT is Internet-based pervasive computing, which created significant development in the recent disposition of IoT infrastructures. The IoT infrastructures lead, manage and generate large amounts of data across various applications including environmental, transportation and healthcare monitoring. In this regard, there are salient uncertainties about the use of security concepts that are frequently measured as a major concern of IoT distributed architecture design. This paper mainly focuses on the classification of IoT, novel architecture considering the sensitivity of data, IoT security layers, review of security issues and acclaimed countermeasures.

Dual Monitoring Communication for Self-Aware Network-on-Chip

2012 ◽  
Vol 3 (3) ◽  
pp. 72-91
Author(s):  
Liang Guang ◽  
Ethiopia Nigussie ◽  
Juha Plosila ◽  
Hannu Tenhunen
Keyword(s):  
High Speed ◽  
Data Communication ◽  
Cmos Technology ◽  
Network On Chip ◽  
Time Profile ◽  
Self Awareness ◽  
Monitoring Networks ◽  
Communication Architecture ◽  
Run Time ◽  
On Chip

Self-aware and adaptive Network-on-Chip (NoC) with dual monitoring networks is presented. Proper monitoring interface is an essential prerequisite to adaptive system reconfiguration in parallel on-chip computing. This work proposes a DMC (dual monitoring communication) architecture to support self-awareness on the NoC platform. One type of monitoring communication is integrated with data channel, in order to trace the run-time profile of data communication in high-speed on-chip networking. The other type is separate from the data communication, and is needed to report the run-time profile to the supervising monitor. Direct latency monitoring on mesochronous NoC is presented as a case study and is directly traced in the integrated communication with a novel latency monitoring table in each router. The latency information is reported by the separate monitoring communication to the supervising monitor, which reconfigures the system to adjust the latency, for instance by dynamic voltage and frequency scaling. With quantitative evaluation using synthetic traces and real applications, the effectiveness and efficiency of direct latency monitoring with DMC architecture is demonstrated. The area overhead of DMC architecture is estimated to be small in 65nm CMOS technology.

Towards the Integration of Blockchain and IoT for Security Challenges in IoT

2020 ◽  
pp. 45-67 ◽  
Author(s):  
K. Dinesh Kumar ◽  
Venkata Rathnam T. ◽  
Venkata Ramana R. ◽  
M. Sudhakara ◽  
Ravi Kumar Poluru
Keyword(s):  
Internet Of Things ◽  
Security Management ◽  
Vital Role ◽  
Management Systems ◽  
Iot Security ◽  
Communication Architecture ◽  
Secure Systems ◽  
Security Issues ◽  
Blockchain Technology ◽  
Iot Devices

Internet of things (IoT) technology plays a vital role in the current technologies because IoT develops a network by integrating different kinds of objects and sensors to create the communication among objects directly without human interaction. With the presence of internet of things technology in our daily comes smart thinking and various advantages. At the same time, secure systems have been a most important concern for the protection of information systems and networks. However, adopting traditional security management systems in the internet of things leads several issues due to the limited privacy and policies like privacy standards, protocol stacks, and authentication rules. Usually, IoT devices has limited network capacities, storage, and computing processors. So they are having more chances to attacks. Data security, privacy, and reliability are three main challenges in the IoT security domain. To address the solutions for the above issues, IoT technology has to provide advanced privacy and policies in this large incoming data source. Blockchain is one of the trending technologies in the privacy management to provide the security. So this chapter is focused on the blockchain technologies which can be able to solve several IoT security issues. This review mainly focused on the state-of-the-art IoT security issues and vulnerabilities by existing review works in the IoT security domains. The taxonomy is presented about security issues in the view of communication, architecture, and applications. Also presented are the challenges of IoT security management systems. The main aim of this chapter is to describe the importance of blockchain technology in IoT security systems. Finally, it highlights the future directions of blockchain technology roles in IoT systems, which can be helpful for further improvements.

scholarly journals A Uniform Architecture Design for Accelerating 2D and 3D CNNs on FPGAs

Electronics ◽  
2019 ◽  
Vol 8 (1) ◽  
pp. 65 ◽  
Author(s):  
Zhiqiang Liu ◽  
Paul Chow ◽  
Jinwei Xu ◽  
Jingfei Jiang ◽  
Yong Dou ◽  
...  
Keyword(s):  
Design Space ◽  
State Of The Art ◽  
Three Dimensional ◽  
Architecture Design ◽  
Computer Vision Applications ◽  
Computationally Intensive ◽  
On Chip ◽  
3D Cnn ◽  
High Level ◽  
2D And 3D

Three-dimensional convolutional neural networks (3D CNNs) have gained popularity in many complicated computer vision applications. Many customized accelerators based on FPGAs are proposed for 2D CNNs, while very few are for 3D CNNs. Three-D CNNs are far more computationally intensive and the design space for 3D CNN acceleration has been further expanded since one more dimension is introduced, making it a big challenge to accelerate 3D CNNs on FPGAs. Motivated by the finding that the computation patterns of 2D and 3D CNNs are very similar, we propose a uniform architecture design for accelerating both 2D and 3D CNNs in this paper. The uniform architecture is based on the idea of mapping convolutions to matrix multiplications. A customized mapping module is developed to generate the feature matrix tilings with no need to store the entire enlarged feature matrix on-chip or off-chip, a splitting strategy is adopted to reconstruct a convolutional layer to adapt to the on-chip memory capacity, and a 2D multiply-and-accumulate (MAC) array is adopted to compute matrix multiplications efficiently. For demonstration, we implement an accelerator prototype with a high-level synthesis (HLS) methodology on a Xilinx VC709 board and test the accelerator on three typical CNN models: AlexNet, VGG16, and C3D. Experimental results show that the accelerator achieves state-of-the-art throughput performance on both 2D and 3D CNNs, with much better energy efficiency than the CPU and GPU.

Sign in / Sign up

Export Citation Format

Share Document