scholarly journals A quad-form clustered mapping approach for large-scale applications of reconfigurable computing systems

2022 ◽  
Vol 97 ◽  
pp. 107637
Author(s):  
Seyed Mehdi Mohtavipour ◽  
Hadi Shahriar Shahhoseini
2021 ◽  
Vol 11 (12) ◽  
pp. 5458
Author(s):  
Sangjun Kim ◽  
Kyung-Joon Park

A cyber-physical system (CPS) is the integration of a physical system into the real world and control applications in a computing system, interacting through a communications network. Network technology connecting physical systems and computing systems enables the simultaneous control of many physical systems and provides intelligent applications for them. However, enhancing connectivity leads to extended attack vectors in which attackers can trespass on the network and launch cyber-physical attacks, remotely disrupting the CPS. Therefore, extensive studies into cyber-physical security are being conducted in various domains, such as physical, network, and computing systems. Moreover, large-scale and complex CPSs make it difficult to analyze and detect cyber-physical attacks, and thus, machine learning (ML) techniques have recently been adopted for cyber-physical security. In this survey, we provide an extensive review of the threats and ML-based security designs for CPSs. First, we present a CPS structure that classifies the functions of the CPS into three layers: the physical system, the network, and software applications. Then, we discuss the taxonomy of cyber-physical attacks on each layer, and in particular, we analyze attacks based on the dynamics of the physical system. We review existing studies on detecting cyber-physical attacks with various ML techniques from the perspectives of the physical system, the network, and the computing system. Furthermore, we discuss future research directions for ML-based cyber-physical security research in the context of real-time constraints, resiliency, and dataset generation to learn about the possible attacks.


Author(s):  
Vinay Sriram ◽  
David Kearney

High speed infrared (IR) scene simulation is used extensively in defense and homeland security to test sensitivity of IR cameras and accuracy of IR threat detection and tracking algorithms used commonly in IR missile approach warning systems (MAWS). A typical MAWS requires an input scene rate of over 100 scenes/second. Infrared scene simulations typically take 32 minutes to simulate a single IR scene that accounts for effects of atmospheric turbulence, refraction, optical blurring and charge-coupled device (CCD) camera electronic noise on a Pentium 4 (2.8GHz) dual core processor [7]. Thus, in IR scene simulation, the processing power of modern computers is a limiting factor. In this paper we report our research to accelerate IR scene simulation using high performance reconfigurable computing. We constructed a multi Field Programmable Gate Array (FPGA) hardware acceleration platform and accelerated a key computationally intensive IR algorithm over the hardware acceleration platform. We were successful in reducing the computation time of IR scene simulation by over 36%. This research acts as a unique case study for accelerating large scale defense simulations using a high performance multi-FPGA reconfigurable computer.


Integration ◽  
2019 ◽  
Vol 65 ◽  
pp. 97-103 ◽  
Author(s):  
Yu-Fan Chiang ◽  
Wei-Yu Chien ◽  
Yue-Der Chih ◽  
Jonathan Chang ◽  
Chrong Jung Lin ◽  
...  

Author(s):  
Arvind Singh Rawat ◽  
Arti Rana ◽  
Adesh Kumar ◽  
Ashish Bagwari

Basic hardware comprehension of an artificial neural network (ANN), to a major scale depends on the proficientrealization of a distinctneuron. For hardware execution of NNs, mostly FPGA-designed reconfigurable computing systems are favorable .FPGA comprehension of ANNs through a hugeamount of neurons is mainlyan exigentassignment. This workconverses the reviews on various research articles of neural networks whose concernsfocused in execution of more than one input neuron and multilayer with or without linearity property by using FPGA. An execution technique through reserve substitution isprojected to adjust signed decimal facts. A detailed review of many research papers have been done for the <br /> proposed work.


Author(s):  
I. I. Levin ◽  
M. D. Chekina

The developed fractal image compression method, implemented for reconfigurable computing systems is described. The main idea parallel fractal image compression based on parallel execution pairwise comparison of domain and rank blocks. Achievement high performance occurs at the expense of simultaneously comparing maximum number of pairs. Implementation fractal image compression for reconfigurable computing systems has two critical resources, as number of input channels and FPGA Look-up Table (LUT). The main critical resource for fractal image compression is data channels, and implementation this task for reconfigurable computing systems requires parallel-pipeline computations organization replace parallel, preliminarily produced performance reduction parallel computational structure. The main critical resource for fractal image compression is data channels, and implementation this task for reconfigurable computing systems requires parallel-pipeline computations organization replace parallel computations organiation. For using parallel-pipeline computations organization, preliminarily have produce performance reduction parallel computational structure. Each operator has routed to computational structure sequentially (bit by bit) to save computational resources and reduces equipment downtime. Storing iterated functions system coefficients for image encoding has been introduced in data structure, which correlates between corresponding parameters the numbers of rank and domain blocks. Applying this approach for parallel-pipeline programs allows scaling computing structure to plurality programmable logic arrays (FPGAs). Task implementation on the reconfigurable computer system Tertius-2 containing eight FPGAs 15 000 times provides performed acceleration relatively with universal multi-core processor, and 18 – 25 times whit to existing solutions for FPGAs.


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