scholarly journals A Low Area High Speed FPGA Implementation of AES Architecture for Cryptography Application

Electronics ◽  
2021 ◽  
Vol 10 (16) ◽  
pp. 2023
Author(s):  
Thanikodi Manoj Kumar ◽  
Kasarla Satish Reddy ◽  
Stefano Rinaldi ◽  
Bidare Divakarachari Parameshachari ◽  
Kavitha Arunachalam
Keyword(s):  
Data Security ◽  
High Speed ◽  
Fpga Implementation ◽  
Digital Data ◽  
Low Area ◽  
Aes Algorithm ◽  
Field Programmable ◽  
Hardware Architectures ◽  
Cyber Crimes ◽  
The Look

Nowadays, a huge amount of digital data is frequently changed among different embedded devices over wireless communication technologies. Data security is considered an important parameter for avoiding information loss and preventing cyber-crimes. This research article details the low power high-speed hardware architectures for the efficient field programmable gate array (FPGA) implementation of the advanced encryption standard (AES) algorithm to provide data security. This work does not depend on the look up tables (LUTs) for the implementation the SubBytes and InvSubBytes stages of transformations of the AES encryption and decryption; this new architecture uses combinational logical circuits for implementing SubBytes and InvSubBytes transformation. Due to the elimination of LUTs, unwanted delays are eliminated in this architecture and a subpipelining structure is introduced for improving the speed of the AES algorithm. Here, modified positive polarity reed muller (MPPRM) architecture is inserted to reduce the total hardware requirements, and comparisons are made with different implementations. With MPPRM architecture introduced in SubBytes stages, an efficient mixcolumn and invmixcolumn architecture that is suited to subpipelined round units is added. The performances of the proposed AES-MPPRM architecture is analyzed in terms of number of slice registers, flip flops, number of slice LUTs, number of logical elements, slices, bonded IOB, operating frequency and delay. There are five different AES architectures including LAES, AES-CTR, AES-CFA, AES-BSRD, and AES-EMCBE. The LUT of the AES-MPPRM architecture designed in the Spartan 6 is reduced up to 15.45% when compared to the AES-BSRD.

Hardware Implementation of AES Algorithm with Logic S-box

2017 ◽  
Vol 26 (09) ◽  
pp. 1750141 ◽  
Author(s):  
Soufiane Oukili ◽  
Seddik Bri
Keyword(s):  
Data Security ◽  
High Speed ◽  
Hardware Implementation ◽  
Network Applications ◽  
Aes Algorithm ◽  
Communication Techniques ◽  
High Speed Network ◽  
Cryptographic Algorithm ◽  
Hardware Implementations ◽  
Field Programmable

Cryptography has an important role in data security against known attacks and decreases or limits the risks of hacking information, especially with rapid growth in communication techniques. In the recent years, we have noticed an increasing requirement to implement cryptographic algorithms in fast rising high-speed network applications. In this paper, we present high throughput efficient hardware implementations of Advanced Encryption Standard (AES) cryptographic algorithm. We have adopted pipeline technique in order to increase the speed and the maximum operating frequency. Therefore, registers are inserted in optimal placements. Furthermore, we have proposed 5-stage pipeline S-box design using combinational logic to reach further speed. In addition, efficient key expansion architecture suitable for our proposed design is also presented. In order to secure the hardware implementation against side-channel attacks, masked S-box is introduced. The implementations had been successfully done by virtex-6 (xc6vlx240t) Field-Programmable Gate Array (FPGA) device using Xilinx ISE 14.7. Our proposed unmasked and masked architectures are very fast, they achieve a throughput of 93.73 Gbps and 58.57 Gbps, respectively. The obtained results are competitive in comparison with the implementations reported in the literature.

scholarly journals Novel Binary Signed-Digit Addition Algorithm for FPGA Implementation

2019 ◽  
Vol 29 (09) ◽  
pp. 2050136
Author(s):  
Yuuki Tanaka ◽  
Yuuki Suzuki ◽  
Shugang Wei
Keyword(s):  
Field Programmable Gate Array ◽  
High Speed ◽  
Number System ◽  
Logic Circuit ◽  
Fpga Implementation ◽  
Number Representation ◽  
Representation System ◽  
Representation Systems ◽  
Field Programmable ◽  
Gate Array

Signed-digit (SD) number representation systems have been studied for high-speed arithmetic. One important property of the SD number system is the possibility of performing addition without long carry chain. However, many numbers of logic elements are required when the number representation system and such an adder are realized on a logic circuit. In this study, we propose a new adder on the binary SD number system. The proposed adder uses more circuit area than the conventional SD adders when those adders are realized on ASIC. However, the proposed adder uses 20% less number of logic elements than the conventional SD adder when those adders are realized on a field-programmable gate array (FPGA) which is made up of 4-input 1-output LUT such as Intel Cyclone IV FPGA.

scholarly journals Low-Power Low-Area architecture of Probability Density Function Estimation for Histogram Equalization

2021 ◽  
pp. 418-427
Author(s):  
Koteswar Rao Bonagiri ◽  
Giri Babu Kande ◽  
P. Chandrasekhar Reddy
Keyword(s):  
Probability Density ◽  
Complex Function ◽  
Histogram Equalization ◽  
Critical Issue ◽  
Function Estimation ◽  
Low Area ◽  
Accessible Information ◽  
Field Programmable ◽  
Mining Design ◽  
The Look

Estimation of Probability Density Functions (PDFs) in view of accessible information is critical issue emerging in various fields, for example, broadcast communications, machine learning, information mining, design pattern recognition and Personal Computer (PC) vision. In this paper, the Look-Up Table–Carry Select Adder-PDF (LUT-CSLA-PDF) mehod is implemented to increase system performance. The LUT is one of the fast way to recognize a complex function in the digital logic circuit. In this work, The FPGA (field programmable gate array) analysis, LUT, slices, flip flops, frequency are improved as well as ASIC (application specified integrated chip) implementation analysis an area, power, delay, Area Power Product (APP), Area Delay Product (ADP) are enhanced in LUT-CSLA-PDF technique compared to conventional methods.

An Efficient Genetic Encoding Scheme for Multiplierless Color Space Converter Design

2013 ◽  
Vol 284-287 ◽  
pp. 3015-3019
Author(s):  
Ching Yi Chen ◽  
Ching Han Chen ◽  
Chih Hao Ma ◽  
Po Yi Wu
Keyword(s):  
Video Compression ◽  
Video Processing ◽  
High Speed ◽  
Color Space ◽  
Low Complexity ◽  
Evolvable Hardware ◽  
Low Area ◽  
Design And Synthesis ◽  
Ycbcr Color Space ◽  
Field Programmable

Color space conversion has become a very important role in image and video processing systems. To speed up some processing processes, many communication and multimedia video compression schemes use luminance-chrominance type color spaces, such as YCbCr or YUV, making a mechanism for converting between different formats necessary. Therefore, techniques which efficiently implement this conversion are desired. For the recent years, a new field of research called Evolvable Hardware (EHW) has emerged which combines aspects of evolutionary computation with hardware design and synthesis. It is a new scheme inspired by natural evolution, for automatic design of hardware systems. This paper presents a novel evolutionary approach for efficient implementation of a RGB to YCbCr color space converter suitable for Field Programmable Gate Array (FPGAs) and VLSI. In the proposed method, we use the genetic algorithm to automatically evolve the multiplierless architecture of the color space converter. The architecture employs only a few shift and addition operations to replace the complex multiplications. The experimental results represent that the performance of implemented architecture is good at RGB to YCbCr color space converting, and it also has the advantages of high-speed, low-complexity, and low-area.

scholarly journals Design of High Speed and Low Area Confined Multiplier on FPGA

2021 ◽  
Vol 11 (4) ◽  
pp. 2736-2746
Author(s):  
Kandagatla Ravi Kumar ◽  
Cheeli Priyadarshini ◽  
Kanakam Bhavani ◽  
Ankam Varun Sundar Kumar ◽  
Palanki Naga Nanda Sai
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
Field Programmable Gate Array ◽  
High Speed ◽  
Digital Signal ◽  
Low Area ◽  
Field Programmable ◽  
Dsp Applications ◽  
Advanced Applications ◽  
Main Factor

In this Advanced world, Technology is playing the major role. Most importantly development in Electronics field has a large impact on the improved life style. Among the advanced applications, DSP ranks first in place. Multipliers are the most basic elements that are widely used in the Digital Signal Processing (DSP) applications. Therefore, the design of the multiplier is the main factor for the performance of the device. Using RTL simulation and a Field Programmable Gate Array (FPGA), we compare the performance of a serial multiplier with an advanced multiplier. Many single bit adders are removed and replaced with multiplexers in this project. So that the less often used FPGAs are fully used by occupying fewer divisions and slices. The use of multiplier architecture results in significant reductions in FPGA resources, latency, area, and power. These multiplication approaches are created utilizing RTL simulation in Xilinx ISE simulator and synthesis in Xilinx ISE 14.7. Finally, the Spartan 3E FPGA is used to implement the design.

scholarly journals Design Space Exploration for High-Speed Implementation of the MISTY1 Block Cipher

2021 ◽  
Vol 2021 ◽  
pp. 1-14
Author(s):  
Raza Hasan ◽  
Yasir Khizar ◽  
Salman Mahmood ◽  
Muhammad Kashif Sheikh
Keyword(s):  
High Speed ◽  
Design Space Exploration ◽  
Block Cipher ◽  
Design Space ◽  
High Efficiency ◽  
Space Exploration ◽  
Wireless Applications ◽  
Low Area ◽  
Field Programmable ◽  
Very High

This paper proposes 2 × unrolled high-speed architectures of the MISTY1 block cipher for wireless applications including sensor networks and image encryption. Design space exploration is carried out for 8-round MISTY1 utilizing dual-edge trigger (DET) and single-edge trigger (SET) pipelines to analyze the tradeoff w.r.t. speed/area. The design is primarily based on the optimized implementation of lookup tables (LUTs) for MISTY1 and its core transformation functions. The LUTs are designed by logically formulating S9/S7 s-boxes and FI and {FO + 32-bit XOR} functions with the fine placement of pipelines. Highly efficient and high-speed MISTY1 architectures are thus obtained and implemented on the field-programmable gate array (FPGA), Virtex-7, XC7VX690T. The high-speed/very high-speed MISTY1 architectures acquire throughput values of 25.2/43 Gbps covering an area of 1331/1509 CLB slices, respectively. The proposed MISTY1 architecture outperforms all previous MISTY1 implementations indicating high speed with low area achieving high efficiency value. The proposed architecture had higher efficiency values than the existing AES and Camellia architectures. This signifies the optimizations made for proposed high-speed MISTY1 architectures.

scholarly journals FPGA Implementation of High Speed Low Area DWT Based Invisible Image Watermarking Algorithm

2012 ◽  
Vol 30 ◽  
pp. 266-273 ◽  
Author(s):  
P Karthigaikumar ◽  
Anumol ◽  
K Baskaran
Keyword(s):  
High Speed ◽  
Image Watermarking ◽  
Fpga Implementation ◽  
Low Area
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