A High-Speed Fully Differential Telescopic Op-Amp for Active Filter Designs in V2X Applications

In this paper, an ultra-wideband fully differential two-stage telescopic 65-nm CMOS op-amp is presented, which uses low-voltage design techniques such as level shifter circuits and low-voltage cascode current mirrors. The designed op-amp consists of two stages. While the telescopic first stage provides high speed and low swing, the second stage provides high gain and large swing. Common-mode feedback circuits (CMFB), which contain five transistors OTA and sensing resistors, are used to set the first-stage output to a known value. The designed two-stage telescopic operational amplifier has 41.04[Formula: see text]dB lower frequency gain, 1.81[Formula: see text]GHz gain-bandwidth product (GBW) and 51.9∘ phase margin under 5[Formula: see text]pF load capacitance. The design consumes a total current of 11.9[Formula: see text]mA from a 1.2-V supply voltage. Presented fully differential two-stage telescopic op-amp by using low-voltage design techniques is suitable for active filter in vehicle-to-everything (V2X) applications with 120[Formula: see text][Formula: see text]m[Formula: see text]m layout area.

Two-Terminal Electronic Circuits with Controllable Linear NDR Region and Their Applications

Negative differential resistance (NDR) is inherent in many electronic devices, in which, over a specific voltage range, the current decreases with increasing voltage. Semiconductor structures with NDR have several unique properties that stimulate the search for technological and circuitry solutions in developing new semiconductor devices and circuits experiencing NDR features. This study considers two-terminal NDR electronic circuits based on multiple-output current mirrors, such as cascode, Wilson, and improved Wilson, combined with a field-effect transistor. The undoubted advantages of the proposed electronic circuits are the linearity of the current-voltage characteristics in the NDR region and the ability to regulate the value of negative resistance by changing the number of mirrored current sources. We derive equations for each proposed circuit to calculate the NDR region’s total current and differential resistance. We consider applications of NDR circuits for designing microwave single frequency oscillators and voltage-controlled oscillators. The problem of choosing the optimal oscillator topology is examined. We show that the designed oscillators based on NDR circuits with Wilson and improved Wilson multiple-output current mirrors have high efficiency and extremely low phase noise. For a single frequency oscillator consuming 33.9 mW, the phase noise is −154.6 dBc/Hz at a 100 kHz offset from a 1.310 GHz carrier. The resulting figure of merit is −221.6 dBc/Hz. The implemented oscillator prototype confirms the theoretical achievements.

A Novel OTA Architecture Exploiting Current Gain Stages to Boost Bandwidth and Slew-Rate

A novel architecture and design approach which make it possible to boost the bandwidth and slewrate performance of operational transconductance amplifiers (OTAs) are proposed and employed to design a low-power OTA with top-of-class small-signal and large-signal figures of merit (FOMs). The proposed approach makes it possible to enhance the gain, bandwidth and slew-rate for a given power consumption and capacitive load, achieving more than an order of magnitude better performance than a comparable conventional folded cascode amplifier. Current mirrors with gain and a push–pull topology are exploited to achieve symmetrical sinking and sourcing output currents, and hence class-AB behavior. The resulting OTA was implemented using the 130 nm STMicroelectronics process, with a supply voltage of 1 V and a power consumption of only 1 µW. Simulations with a 200 pF load capacitance showed a gain of 92 dB, a unity-gain frequency of 141 kHz, and a peak slew-rate of 30 V/ms, with a phase margin of 80°, and good noise, PSRR and CMRR performance. The small-signal and large-signal current and power FOMs are the highest reported in the literature for comparable amplifiers. Extensive parametric and Monte Carlo simulations show that the OTA is robust against process, supply voltage and temperature (PVT) variations, as well as against mismatches.

DESIGN AND SIMULATION OF NEURON-EQUIVALENTORS ARRAY FOR CREATION OF SELF-LEARNING EQUIVALENT-CONVOLUTIONAL NEURAL STRUCTURES (SLECNS)

In the paper, we consider the urgent need to create highly efficient hardware accelerators for machine learning algorithms, including convolutional and deep neural networks (CNN and DNNS), for associative memory models, clustering, and pattern recognition. We show a brief overview of our related works the advantages of the equivalent models (EM) for describing and designing bio-inspired systems. The capacity of NN on the basis of EM and of its modifications is in several times quantity of neurons. Such neural paradigms are very perspective for processing, clustering, recognition, storing large size, strongly correlated, highly noised images and creating of uncontrolled learning machine. And since the basic operational functional nodes of EM are such vector-matrix or matrix-tensor procedures with continuous-logical operations as: normalized vector operations “equivalence”, “nonequivalence”, and etc. , we consider in this paper new conceptual approaches to the design of full-scale arrays of such neuron-equivalentors (NEs) with extended functionality, including different activation functions. Our approach is based on the use of analog and mixed (with special coding) methods for implementing the required operations, building NEs (with number of synapsis from 8 up to 128 and more) and their base cells, nodes based on photosensitive elements and CMOS current mirrors. Simulation results show that the efficiency of NEs relative to the energy intensity is estimated at a value of not less than 1012 an. op. / sec on W and can be increased. The results confirm the correctness of the concept and the possibility of creating NE and MIMO structures on their basis.

A Research Perspective on CMOS Current Mirror Circuits: Configurations and Techniques

Background: Immense growth in the field of VLSI technology is fuelled by its feasibility to realize analog circuits in µm and nm technology. Current mirror (CM) is a basic building block used to enhance performance characteristics by constructing the complex analog/mixed-signal circuits like amplifier, data converters and voltage level converters. In addition, the current mirror finds diverse of applications from biasing to current-mode signal processing. Methods: In this paper, the Complementary Metal Oxide Semiconductor (CMOS) technology based current mirror (CM) circuits are discussed with their advantages and disadvantages accompanied by the performance analysis of different parameters. It also briefs on the various techniques which are employed for improvising the current mirror performance like gain boosting and bandwidth extension. Besides, this paper lists the CMs that use different types of MOS devices like Floating Gate MOS, Bulk-driven MOS, and Quasi-Floating Gate MOS. As a result, the paper performs a detailed review on CMOS Current mirrors and its techniques. Results: Basic CM circuits that can act as building blocks in the VLSI circuits are simulated using 0.25 μm, BSIM and Level 1 technology. In addition, various devices based CMs are investigated and compared. Conclusion: The comprehensive discussion shows that the current mirror plays a significant role in analog/mixed-signal circuits design to realize complex systems for low-power biomedical and wireless applications.