Improved on-chip self-triggered single-event transient measurement circuit design and applications

2017 ◽  
Vol 71 ◽  
pp. 99-105 ◽  
Author(s):  
Rongmei Chen ◽  
Wei Chen ◽  
Xiaoqiang Guo ◽  
Chen Shen ◽  
Fengqi Zhang ◽  
...  
Keyword(s):  
Circuit Design ◽  
Single Event ◽  
Measurement Circuit ◽  
Single Event Transient ◽  
On Chip ◽  
Transient Measurement

Research on the effect of single-event transient of an on-chip linear voltage regulator fabricated on 130 nm commercial CMOS technology

2017 ◽  
Vol 73 ◽  
pp. 116-121 ◽  
Author(s):  
QiFeng Zhao ◽  
GuoQing Yang ◽  
YongJie Sun ◽  
PeiFu Yu ◽  
JianJun Chen ◽  
...  
Keyword(s):  
Cmos Technology ◽  
Voltage Regulator ◽  
Single Event ◽  
Single Event Transient ◽  
On Chip ◽  
Linear Voltage

scholarly journals On-Chip Characterization of Single-Event Transient Pulsewidths

2006 ◽  
Vol 6 (4) ◽  
pp. 542-549 ◽  
Author(s):  
Balaji Narasimham ◽  
Vishwa Ramachandran ◽  
Bharat L. Bhuva ◽  
Ronald D. Schrimpf ◽  
Arthur F. Witulski ◽  
...  
Keyword(s):  
Single Event ◽  
Single Event Transient ◽  
On Chip

A SEE Hardened Read-Out Circuit of EEPROM for Space Application

2012 ◽  
Vol 198-199 ◽  
pp. 1105-1109
Author(s):  
Xin Jie Zhou ◽  
Jing He Wei ◽  
Lei Lei Li
Keyword(s):  
Circuit Design ◽  
Space Application ◽  
Single Event Upset ◽  
Single Event ◽  
Single Event Transient ◽  
Single Event Effect ◽  
Radiation Hardened

As wide application of EEPROM devices in space and military field, more and more researches focus on its radiation hardened characteristics in international. To improve the single-event effect (SEE) tolerant ability of read-out circuits in the memory, a radiation hardened circuit is designed. The design kernels of radiation hardened latch-flip are given and designed to resist the single-event upset (SEU) effect. A correction circuit is proposed to resist the single-event transient (SET) effect. The performances of this design are: SEU (LET)th ≥ 27 MeV•cm2/mg, SEL(LET)th ≥ 75 MeV•cm2/mg , read out time ≤200 ns. The new design not only satisfied the needs of present work, but supplies a worthful reference for radiation hardened circuit design in future.

Supply Voltage Dependent On-Chip Single-Event Transient Pulse Shape Measurements in 90-nm Bulk CMOS Under Alpha Irradiation

2013 ◽  
Vol 60 (4) ◽  
pp. 2640-2646 ◽  
Author(s):  
Michael Hofbauer ◽  
Kurt Schweiger ◽  
Horst Zimmermann ◽  
Ulrich Giesen ◽  
Frank Langner ◽  
...  
Keyword(s):  
Pulse Shape ◽  
Supply Voltage ◽  
Single Event ◽  
Single Event Transient ◽  
Voltage Dependent ◽  
On Chip ◽  
Alpha Irradiation

scholarly journals Bulk Bias as an Analog Single-Event Transient Mitigation Technique with Negligible Penalty

Electronics ◽  
2019 ◽  
Vol 9 (1) ◽  
pp. 27
Author(s):  
Jingtian Liu ◽  
Qian Sun ◽  
Bin Liang ◽  
Jianjun Chen ◽  
Yaqing Chi ◽  
...  
Keyword(s):  
Circuit Design ◽  
Analog Circuits ◽  
Analog Circuit ◽  
Forward Bias ◽  
Cmos Technology ◽  
Common Source ◽  
Single Event ◽  
Single Event Transient ◽  
Body Effect ◽  
Radiation Hardened

In analog circuit design, the bulks of MOSFETs can be tied to their respective sources to remove body effect. This paper models and analyzes the sensitivity of single-event transients (SETs) in common source (CS) amplifier with bulk tied to source (BTS) in 40 nm twin-well bulk CMOS technology. The simulation results present that the proposed BTS radiation-hardened-by-design (RHBD) technique can reduce charge collection and suppress the SET induced perturbation effectively in various input conditions of the circuit. The detailed analysis shows that the mitigation of SET is primarily due to the forward-bias of bulk potential. This technique is universally applicable in radiation-hardening design for analog circuits with negligible penalty.

Single Event Transient (SET) Mitigation Circuits with Immune Leaf Nodes

2021 ◽  
pp. 1-1
Author(s):  
Faisal Mustafa Sajjade ◽  
Neeraj Kumar Goyal ◽  
B.K.S.V.L Varaprasad
Keyword(s):  
Single Event ◽  
Single Event Transient
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