Circuit simulation assisting Physical Fault Isolation for effective root cause analysis

2017 ◽  
Vol 76-77 ◽  
pp. 194-200 ◽  
Author(s):  
M. Boostandoost ◽  
D. Gräfje ◽  
F. Pop
Keyword(s):  
Circuit Simulation ◽  
Root Cause Analysis ◽  
Fault Isolation ◽  
Cause Analysis ◽  
Root Cause

Root Cause Analysis Techniques Using Picosecond Time Resolved LADA

2014 ◽  
Author(s):  
Dan Bodoh ◽  
Kent Erington ◽  
Kris Dickson ◽  
George Lange ◽  
Carey Wu ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Picosecond Laser ◽  
Root Cause Analysis ◽  
Fault Isolation ◽  
Time Resolved ◽  
Cause Analysis ◽  
Root Cause ◽  
Design And Manufacturing ◽  
Multiple Interactions ◽  
Established Technique

Abstract Laser-assisted device alteration (LADA) is an established technique used to identify critical speed paths in integrated circuits. LADA can reveal the physical location of a speed path, but not the timing of the speed path. This paper describes the root cause analysis benefits of 1064nm time resolved LADA (TR-LADA) with a picosecond laser. It shows several examples of how picosecond TR-LADA has complemented the existing fault isolation toolset and has allowed for quicker resolution of design and manufacturing issues. The paper explains how TR-LADA increases the LADA localization resolution by eliminating the well interaction, provides the timing of the event detected by LADA, indicates the propagation direction of the critical signals detected by LADA, allows the analyst to infer the logic values of the critical signals, and separates multiple interactions occurring at the same site for better understanding of the critical signals.

Challenges of System Level Failure Analysis of Electronics in the Automotive Industry

2017 ◽  
Author(s):  
Bence Hevesi
Keyword(s):  
Failure Analysis ◽  
Case Studies ◽  
Automotive Industry ◽  
Root Cause Analysis ◽  
Fault Isolation ◽  
System Level ◽  
Cause Analysis ◽  
Root Cause ◽  
Analysis Workflow

Abstract In this paper, different failure analysis (FA) workflows are showed which combines different FA approaches for fast and efficient fault isolation and root cause analysis in system level products. Two case studies will be presented to show the importance of a well-adjusted failure analysis workflow.

Root Cause Analysis of High Input Offset Voltage in Mixed-Signal Design Through Nanoprobing and Cadence Simulation

2019 ◽  
Author(s):  
Zhenni Wan ◽  
Weikai Yin ◽  
Yining Zang ◽  
Madhukar Karigerasi ◽  
Saurabh Kulkarni ◽  
...  
Keyword(s):  
Failure Modes ◽  
Root Cause Analysis ◽  
Fault Isolation ◽  
The Body ◽  
Cause Analysis ◽  
Mixed Signal ◽  
Root Cause ◽  
Offset Voltage ◽  
Amplifier Gain ◽  
Mixed Signal Ic

Abstract Root cause analysis of parametric failures in mixed-signal IC designs has been a challenging topic due to the marginality of failure modes. This work presents two case studies of offset voltage (Vos) failures which are commonly seen in mixed-signal IC designs. Nanoprobing combined with Cadence simulation becomes a powerful methodology in fault isolation. Large Vos is typically caused by the mismatch of electrical properties of the components on two balanced rails. In our first case, we present a case-study of nanoprobing combined with bench test and Cadence simulation to debug the root cause of a class-D amplifier voltage offset related yield loss from mixedsignal design sensitivity. Bench electrical measurements confirm the dependency of offset voltage (Vos) on boost voltage (VBST) and amplifier gain settings, which isolates the root cause from mismatch in amplifier gain resistors. The bench measurements match extremely well when an extra parasitic resistance is added to the input of the amplifier in the Cadence simulation. Kelvin 4 points nanoprobing on the amplifier input matching resistors confirmed a 40% mismatch as a result of both layout sensitivity and fabrication. This case highlights that the role of nanoprobing combined with Cadence simulation is not only valuable in physical failure root cause analysis but also in providing guidance to a potential process fix for current and future designs. In our second case, a decrease in offset voltage (Vos) is found through bench validation by reducing the supply voltage (VDD), suggesting a new mismatch mechanism related to the body-source bias. Nanoprobing of the input PMOS transistors clearly shows humps in the subthreshold region of IV characteristics, and the severity of humps increases with body-source bias. Vos derived from the nanoprobing results aligns well with the bench data, suggesting hump effect to be the root cause of Vos deviation. This study suggests that by combining Cadence simulation and nanoprobing in the failure analysis process of parametric failures, suspicious problematic devices can be identified more easily, greatly reducing the need for trial and error.

Root Cause analysis of SG tube ODSCC indications within the tube sheets of NPP biblis unit A

2011 ◽  
pp. 78-86
Author(s):  
R. Kilian ◽  
J. Beck ◽  
H. Lang ◽  
V. Schneider ◽  
T. Schönherr ◽  
...  
Keyword(s):  
Root Cause Analysis ◽  
Cause Analysis ◽  
Root Cause

Rule Construction and its Execution for Root Cause Analysis

2012 ◽  
Vol 132 (10) ◽  
pp. 1689-1697
Author(s):  
Yutaka Kudo ◽  
Tomohiro Morimura ◽  
Kiminori Sugauchi ◽  
Tetsuya Masuishi ◽  
Norihisa Komoda
Keyword(s):  
Root Cause Analysis ◽  
Cause Analysis ◽  
Root Cause

Root Cause Analysis for Pin Leakage

2016 ◽  
Author(s):  
Zhigang Song ◽  
Jochonia Nxumalo ◽  
Manuel Villalobos ◽  
Sweta Pendyala
Keyword(s):  
Failure Analysis ◽  
Root Cause Analysis ◽  
Advanced Technology ◽  
Process Step ◽  
Cause Analysis ◽  
Hard Mask ◽  
Technology Node ◽  
Root Cause ◽  
Tools And Techniques

Abstract Pin leakage continues to be on the list of top yield detractors for microelectronics devices. It is simply manifested as elevated current with one pin or several pins during pin continuity test. Although many techniques are capable to globally localize the fault of pin leakage, root cause analysis and identification for it are still very challenging with today’s advanced failure analysis tools and techniques. It is because pin leakage can be caused by any type of defect, at any layer in the device and at any process step. This paper presents a case study to demonstrate how to combine multiple techniques to accurately identify the root cause of a pin leakage issue for a device manufactured using advanced technology node. The root cause was identified as under-etch issue during P+ implantation hard mask opening for ESD protection diode, causing P+ implantation missing, which was responsible for the nearly ohmic type pin leakage.

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