Challenges of System Level Failure Analysis of Electronics in the Automotive Industry

Author(s):  
Bence Hevesi

Abstract In this paper, different failure analysis (FA) workflows are showed which combines different FA approaches for fast and efficient fault isolation and root cause analysis in system level products. Two case studies will be presented to show the importance of a well-adjusted failure analysis workflow.

Author(s):  
Dan Bodoh ◽  
Kent Erington ◽  
Kris Dickson ◽  
George Lange ◽  
Carey Wu ◽  
...  

Abstract Laser-assisted device alteration (LADA) is an established technique used to identify critical speed paths in integrated circuits. LADA can reveal the physical location of a speed path, but not the timing of the speed path. This paper describes the root cause analysis benefits of 1064nm time resolved LADA (TR-LADA) with a picosecond laser. It shows several examples of how picosecond TR-LADA has complemented the existing fault isolation toolset and has allowed for quicker resolution of design and manufacturing issues. The paper explains how TR-LADA increases the LADA localization resolution by eliminating the well interaction, provides the timing of the event detected by LADA, indicates the propagation direction of the critical signals detected by LADA, allows the analyst to infer the logic values of the critical signals, and separates multiple interactions occurring at the same site for better understanding of the critical signals.


Author(s):  
Zhigang Song ◽  
Jochonia Nxumalo ◽  
Manuel Villalobos ◽  
Sweta Pendyala

Abstract Pin leakage continues to be on the list of top yield detractors for microelectronics devices. It is simply manifested as elevated current with one pin or several pins during pin continuity test. Although many techniques are capable to globally localize the fault of pin leakage, root cause analysis and identification for it are still very challenging with today’s advanced failure analysis tools and techniques. It is because pin leakage can be caused by any type of defect, at any layer in the device and at any process step. This paper presents a case study to demonstrate how to combine multiple techniques to accurately identify the root cause of a pin leakage issue for a device manufactured using advanced technology node. The root cause was identified as under-etch issue during P+ implantation hard mask opening for ESD protection diode, causing P+ implantation missing, which was responsible for the nearly ohmic type pin leakage.


Author(s):  
Trevor Bailey ◽  
Suzanne Woll ◽  
Rajul Misra ◽  
Kevin Otto

This paper presents a model-based systems engineering methodology that can be applied to perform a root cause analysis on transient systems. The methodology extends existing root cause analysis best practice by incorporating system modeling and analysis techniques. The methodology is deployed through a detailed 5-step process to understand, identify, assess, FMEA, and validate potential transient system-level root causes. A transient performance reliability analysis for a dual mode refrigeration system is used to demonstrate how the methodology can be applied. The paper also describes a set of success factors for applying the methodology using a phased approach with a large cross-functional team.


Author(s):  
Annamária Koncz ◽  
László Pokorádi ◽  
Zsolt Csaba Johanyák

The automotive industry is one of the most dynamically growing fields of the manufacturingarea. Besides this, it has very strict rules concerning safety and reliability. In our work, our aim is to point out the importance of the automotive industry (based on statistics) and the rules in connection with risk and root cause analysis. The most important risk analysis method is the Failure Mode and Effect Analysis (FMEA). According to standards and OEM regulations, FMEA is obligatory in the automotive sector. In our study, we summarise the area of FMEA usage, its types and process steps.


Author(s):  
Jie Zhu ◽  
An Yan Du ◽  
Bing Hai Liu ◽  
Eddie Er ◽  
Si Ping Zhao ◽  
...  

Abstract In this paper, we report an advanced sample preparation methodology using in-situ lift-out FIB and Flipstage for tridirectional TEM failure analysis. A planar-view and two cross-section TEM samples were prepared from the same target. Firstly, a planar-view lamellar parallel to the wafer surface was prepared using in-situ lift-out FIB milling. Upon TEM analysis, the planar sample was further milled in the along-gate and cross-gate directions separately. Eventually, a pillar-like sample containing a single transistor gate was obtained. Using this technique, we are able to analyze the defect from three perpendicular directions and obtain more information on the defect for failure root-cause analysis. A MOSFETs case study is described to demonstrate the procedure and advantages of this technique.


Author(s):  
Hui Peng Ng ◽  
Angela Teo ◽  
Ghim Boon Ang ◽  
Alfred Quah ◽  
N. Dayanand ◽  
...  

Abstract This paper discussed on how the importance of failure analysis to identify the root cause and mechanism that resulted in the MEMS failure. The defect seen was either directly on the MEMS caps or the CMOS integrated chip in wafer fabrication. Two case studies were highlighted in the discussion to demonstrate how the FA procedures that the analysts had adopted in order to narrow down to the defect site successfully on MEMS cap as well as on CMOS chip on MEMS package units. Besides the use of electrical fault isolation tool/technique such as TIVA for defect localization, a new physical deprocessing approach based on the cutting method was performed on the MEMS package unit in order to separate the MEMS from the Si Cap. This approach would definitely help to prevent the introduction of particles and artifacts during the PFA that could mislead the FA analyst into wrong data interpretation. Other FA tool such as SEM inspection to observe the physical defect and Auger analysis to identify the elements in the defect during the course of analysis were also documented in this paper.


Author(s):  
Jeremy A. Walraven ◽  
Mark W. Jenkins ◽  
Tuyet N. Simmons ◽  
James E. Levy ◽  
Sara E. Jensen ◽  
...  

Abstract Manufacturing of integrated circuits (ICs) using a split foundry process expands design space in IC fabrication by employing unique capabilities of multiple foundries and provides added security for IC designers [1]. Defect localization and root cause analysis is critical to failure identification and implementation of corrective actions. In addition to split-foundry fabrication, the device addressed in this publication is comprised of 8 metal layers, aluminum test pads, and tungsten thru-silicon vias (TSVs) making the circuit area > 68% metal. This manuscript addresses the failure analysis efforts involved in root cause analysis, failure analysis findings, and the corrective actions implemented to eliminate these failure mechanisms from occurring in future product.


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