MXene Ti3C2 memristor for neuromorphic behavior and decimal arithmetic operation applications

Background:: In recent years, there has been a high demand for executing digital signal processing and machine learning applications on energy-constrained devices. Squaring is a vital arithmetic operation used in such applications. Hence, improving the energy efficiency of squaring is crucial. Objective:: In this paper, a novel approximation method based on piecewise linear segmentation of the square function is proposed. Methods: Two-segment, four-segment and eight-segment accurate and energy-efficient 32-bit approximate designs for squaring were implemented using this method. The proposed 2-segment approximate squaring hardware showed 12.5% maximum relative error and delivered up to 55.6% energy saving when compared with state-of-the-art approximate multipliers used for squaring. Results: The proposed 4-segment hardware achieved a maximum relative error of 3.13% with up to 46.5% energy saving. Conclusion:: The proposed 8-segment design emerged as the most accurate squaring hardware with a maximum relative error of 0.78%. The comparison also revealed that the 8-segment design is the most efficient design in terms of error-area-delay-power product.

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Fast Two-Stage Computation of an Index Policy for Multi-Armed Bandits with Setup Delays

Mathematics ◽

10.3390/math9010052 ◽

2020 ◽

Vol 9 (1) ◽

pp. 52

Author(s):

José Niño-Mora

Keyword(s):

Numerical Study ◽

Arithmetic Operation ◽

Bandit Problem ◽

Index Policy ◽

Two Stage ◽

Second Stage ◽

Whittle Index ◽

Set Up ◽

Computing Method ◽

Special Case

We consider the multi-armed bandit problem with penalties for switching that include setup delays and costs, extending the former results of the author for the special case with no switching delays. A priority index for projects with setup delays that characterizes, in part, optimal policies was introduced by Asawa and Teneketzis in 1996, yet without giving a means of computing it. We present a fast two-stage index computing method, which computes the continuation index (which applies when the project has been set up) in a first stage and certain extra quantities with cubic (arithmetic-operation) complexity in the number of project states and then computes the switching index (which applies when the project is not set up), in a second stage, with quadratic complexity. The approach is based on new methodological advances on restless bandit indexation, which are introduced and deployed herein, being motivated by the limitations of previous results, exploiting the fact that the aforementioned index is the Whittle index of the project in its restless reformulation. A numerical study demonstrates substantial runtime speed-ups of the new two-stage index algorithm versus a general one-stage Whittle index algorithm. The study further gives evidence that, in a multi-project setting, the index policy is consistently nearly optimal.

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Error-Correcting Codes in Binary-Coded-Decimal Arithmetic

IEEE Transactions on Computers ◽

10.1109/tc.1978.1674987 ◽

1978 ◽

Vol C-27 (11) ◽

pp. 977-984 ◽

Cited By ~ 2

Author(s):

Chao-Kai Liu ◽

Tse Lin Wang

Keyword(s):

Error Correcting Codes ◽

Decimal Arithmetic

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Binary-Coded Decimal Arithmetic Instructions

X86 Assembly Language and C Fundamentals ◽

10.1201/b14582-13 ◽

2013 ◽

pp. 433-468

Keyword(s):

Decimal Arithmetic

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Multiple-Precision BLAS Library for Graphics Processing Units

10.36227/techrxiv.12580301.v1 ◽

2020 ◽

Author(s):

Konstantin Isupov ◽

Vladimir Knyazkov

Keyword(s):

Graphics Processing Units ◽

Arithmetic Operation ◽

Number System ◽

Residue Number System ◽

Floating Point ◽

Data Types ◽

Rounding Errors ◽

Multiple Precision ◽

Graphics Processing ◽

Point Arithmetic

The binary32 and binary64 floating-point formats provide good performance on current hardware, but also introduce a rounding error in almost every arithmetic operation. Consequently, the accumulation of rounding errors in large computations can cause accuracy issues. One way to prevent these issues is to use multiple-precision floating-point arithmetic. This preprint, submitted to Russian Supercomputing Days 2020, presents a new library of basic linear algebra operations with multiple precision for graphics processing units. The library is written in CUDA C/C++ and uses the residue number system to represent multiple-precision significands of floating-point numbers. The supported data types, memory layout, and main features of the library are considered. Experimental results are presented showing the performance of the library.

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A Singular Value Thresholding with Diagonal-Update Algorithm for Low-Rank Matrix Completion

Mathematical Problems in Engineering ◽

10.1155/2020/8812701 ◽

2020 ◽

Vol 2020 ◽

pp. 1-14

Author(s):

Yong-Hong Duan ◽

Rui-Ping Wen ◽

Yun Xiao

Keyword(s):

Matrix Completion ◽

Arithmetic Operation ◽

Computational Cost ◽

Singular Value ◽

Low Rank ◽

Simple Arithmetic ◽

Rank Matrix ◽

Low Rank Matrix Completion ◽

Low Rank Matrix ◽

Singular Value Thresholding

The singular value thresholding (SVT) algorithm plays an important role in the well-known matrix reconstruction problem, and it has many applications in computer vision and recommendation systems. In this paper, an SVT with diagonal-update (D-SVT) algorithm was put forward, which allows the algorithm to make use of simple arithmetic operation and keep the computational cost of each iteration low. The low-rank matrix would be reconstructed well. The convergence of the new algorithm was discussed in detail. Finally, the numerical experiments show the effectiveness of the new algorithm for low-rank matrix completion.

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Motion Control Algorithm Expanding Arithmetic Operation for Low-Cost Microprocessor

Journal of Institute of Control Robotics and Systems ◽

10.5302/j.icros.2012.18.12.1079 ◽

2012 ◽

Vol 18 (12) ◽

pp. 1079-1085

Author(s):

Sang-Chan Moon ◽

Jae-Jun Kim ◽

Kyu-Min Nam ◽

Byoung-Soo Kim ◽

Soon-Geul Lee

Keyword(s):

Motion Control ◽

Control Algorithm ◽

Low Cost ◽

Arithmetic Operation

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Design of delay efficient Booth multiplier using pipelining

International Journal of Engineering & Technology ◽

10.14419/ijet.v7i2.16.11423 ◽

2018 ◽

Vol 7 (2.16) ◽

pp. 94

Author(s):

Abhishek Choubey ◽

SPV Subbarao ◽

Shruti B. Choubey

Keyword(s):

Critical Path ◽

Arithmetic Operation ◽

Vlsi Design ◽

Digital Signal ◽

Path Delay ◽

Large Area ◽

Booth Multiplier ◽

Critical Path Delay ◽

Long Latency ◽

Comparison Results

Multiplication is one of the most an essential arithmetic operation used in numerous applications in digital signal processing and communications. These applications need transformations, convolutions and dot products that involve an enormous amount of multiplications of an operand with a constant. Typical examples include wavelet, digital filters, such as FIR or IIR. However, multiplier structures have relatively large area-delay product, long latency and significantly high power consumption compared to other the arithmetic structure. Therefore, low power multiplier design has been always a significant part of DSP structure for VLSI design. The Booth multiplier is promising as the most efficient amongst the others multiplier as it reduces the complexity of considerably than others. In this paper, we have proposed Booth-multiplier using seamless pipelining. Theoretical comparison results show that the proposed Booth multiplier requires less critical path delay compared to traditional Booth multiplier. ASIC simulation results show proposed radix-16 Booth multiplier 13% less critical path delay for word width n=16 and 17% less critical path delay compared for bit width n=32 to best existing radix-16 Booth multiplier.

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